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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-08 19:38:54 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-08 19:38:54 +0100 |
| commit | f45ce4c35f5e0873bbbc3119eff8539610233b7e (patch) | |
| tree | 28e00c540fdb80e6ea4bafe0619ee783a4a28315 /target/arm/translate-sve.c | |
| parent | 5e79887ba67e22bfd890b72f94c482176a200fbc (diff) | |
| download | qemu-f45ce4c35f5e0873bbbc3119eff8539610233b7e.zip qemu-f45ce4c35f5e0873bbbc3119eff8539610233b7e.tar.gz qemu-f45ce4c35f5e0873bbbc3119eff8539610233b7e.tar.bz2 | |
target/arm: Rename TBFLAG_A64 ZCR_LEN to VL
With SME, the vector length does not only come from ZCR_ELx.
Comment that this is either NVL or SVL, like the pseudocode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
| -rw-r--r-- | target/arm/translate-sve.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 836511d..67761bf 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -111,7 +111,7 @@ static inline int pred_full_reg_offset(DisasContext *s, int regno) /* Return the byte size of the whole predicate register, VL / 64. */ static inline int pred_full_reg_size(DisasContext *s) { - return s->sve_len >> 3; + return s->vl >> 3; } /* Round up the size of a register to a size allowed by |