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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:24 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:51 +0100 |
| commit | 7dbfafc157290b52af6109b82b8398d10ef5c3b3 (patch) | |
| tree | e74929c5054c72d53d8cb33df5a338b122d4cc38 /target/arm/translate-sve.c | |
| parent | 598ab0b24c0cb807b3f380ab422915dd6c229026 (diff) | |
| download | qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.zip qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.gz qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.bz2 | |
target/arm: Implement REVD
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
| -rw-r--r-- | target/arm/translate-sve.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 24ffb69..9ed3b26 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -2901,6 +2901,8 @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0) +TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a, 0) + TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) |