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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-17 10:43:44 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-22 14:44:54 +0100 |
| commit | 01d90db59978731e35c97ead30d891829929867d (patch) | |
| tree | 8dd544ac88245acde522c022eeb45122496dfe94 /target/arm/translate-m-nocp.c | |
| parent | c89a9d139bc8ba39c0d88840da47cc69ff9037d5 (diff) | |
| download | qemu-01d90db59978731e35c97ead30d891829929867d.zip qemu-01d90db59978731e35c97ead30d891829929867d.tar.gz qemu-01d90db59978731e35c97ead30d891829929867d.tar.bz2 | |
target/arm: Use tcg_constant in translate-m-nocp.c
Use tcg_constant_{i32,i64} as appropriate throughout.
This fixes a bug in trans_VSCCLRM() where we were leaking a TCGv.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-m-nocp.c')
| -rw-r--r-- | target/arm/translate-m-nocp.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index d9e144e..27363a7 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) } /* Zero the Sregs from btmreg to topreg inclusive. */ - zero = tcg_const_i64(0); + zero = tcg_constant_i64(0); if (btmreg & 1) { write_neon_element64(zero, btmreg >> 1, 1, MO_32); btmreg++; @@ -187,8 +187,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) } assert(btmreg == topreg + 1); if (dc_isar_feature(aa32_mve, s)) { - TCGv_i32 z32 = tcg_const_i32(0); - store_cpu_field(z32, v7m.vpr); + store_cpu_field(tcg_constant_i32(0), v7m.vpr); } clear_eci_state(s); @@ -512,7 +511,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, } case ARM_VFP_FPCXT_NS: { - TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + TCGv_i32 control, sfpa, fpscr, fpdscr; TCGLabel *lab_active = gen_new_label(); lookup_tb = true; @@ -552,10 +551,9 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, storefn(s, opaque, tmp, true); /* If SFPA is zero then set FPSCR from FPDSCR_NS */ fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); - zero = tcg_const_i32(0); - tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), + fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(zero); tcg_temp_free_i32(sfpa); tcg_temp_free_i32(fpdscr); tcg_temp_free_i32(fpscr); |