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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-14 14:28:27 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-06-05 17:23:09 +0100 |
| commit | 1738860d7e60dec5dbeba17f8b44d31aae3accac (patch) | |
| tree | a6ac3baa3a540ed6723a365c76926932c7992123 /target/arm/translate-a64.h | |
| parent | a04b68e1d4c4f0cd5cd7542697b1b230b84532f5 (diff) | |
| download | qemu-1738860d7e60dec5dbeba17f8b44d31aae3accac.zip qemu-1738860d7e60dec5dbeba17f8b44d31aae3accac.tar.gz qemu-1738860d7e60dec5dbeba17f8b44d31aae3accac.tar.bz2 | |
target/arm: Convert rax1 to gvec helpers
With this conversion, we will be able to use the same helpers
with sve. This also fixes a bug in which we failed to clear
the high bits of the SVE register after an AdvSIMD operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200514212831.31248-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.h')
| -rw-r--r-- | target/arm/translate-a64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index f02fbb6..da0f59a 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -115,4 +115,7 @@ static inline int vec_full_reg_size(DisasContext *s) bool disas_sve(DisasContext *, uint32_t); +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ |