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author | Richard Henderson <richard.henderson@linaro.org> | 2020-05-13 09:32:44 -0700 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-14 15:03:08 +0100 |
commit | 50c160d44eb059c7fc7f348ae2c3b0cb41437044 (patch) | |
tree | af047a9924427cccc34d7172796810b697e62c12 /target/arm/translate-a64.c | |
parent | 525d9b6d42844e187211d25b69be8b378785bc24 (diff) | |
download | qemu-50c160d44eb059c7fc7f348ae2c3b0cb41437044.zip qemu-50c160d44eb059c7fc7f348ae2c3b0cb41437044.tar.gz qemu-50c160d44eb059c7fc7f348ae2c3b0cb41437044.tar.bz2 |
target/arm: Vectorize SABD/UABD
Include 64-bit element size in preparation for SVE2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
-rw-r--r-- | target/arm/translate-a64.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4577df3..54b0655 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11190,6 +11190,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); } return; + case 0xe: /* SABD, UABD */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uabd, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sabd, size); + } + return; case 0x10: /* ADD, SUB */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); @@ -11322,7 +11329,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genenvfn = fns[size][u]; break; } - case 0xe: /* SABD, UABD */ case 0xf: /* SABA, UABA */ { static NeonGenTwoOpFn * const fns[3][2] = { |