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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-25 15:58:15 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 16:43:26 +0100 |
| commit | 458d0ab6830f9bcd76af9df4d1d4db8ab646fcef (patch) | |
| tree | ea4e0e9a7403c9a6272b47ebbe3c362a826de362 /target/arm/translate-a64.c | |
| parent | 5693887f2e97335362d945c778f2bbddd4e9d1bb (diff) | |
| download | qemu-458d0ab6830f9bcd76af9df4d1d4db8ab646fcef.zip qemu-458d0ab6830f9bcd76af9df4d1d4db8ab646fcef.tar.gz qemu-458d0ab6830f9bcd76af9df4d1d4db8ab646fcef.tar.bz2 | |
target/arm: Implement bfloat widening fma (indexed)
This is BFMLAL{B,T} for both AArch64 AdvSIMD and SVE,
and VFMA{B,T}.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8dcb15a..8713dfe 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13472,18 +13472,27 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } + size = MO_32; break; case 1: /* BFDOT */ if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { unallocated_encoding(s); return; } + size = MO_32; + break; + case 3: /* BFMLAL{B,T} */ + if (is_scalar || !dc_isar_feature(aa64_bf16, s)) { + unallocated_encoding(s); + return; + } + /* can't set is_fp without other incorrect size checks */ + size = MO_16; break; default: unallocated_encoding(s); return; } - size = MO_32; break; case 0x11: /* FCMLA #0 */ case 0x13: /* FCMLA #90 */ @@ -13613,6 +13622,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) gen_gvec_op4_ool(s, is_q, rd, rn, rm, rd, index, gen_helper_gvec_usdot_idx_b); return; + case 3: /* BFMLAL{B,T} */ + gen_gvec_op4_fpst(s, 1, rd, rn, rm, rd, 0, (index << 1) | is_q, + gen_helper_gvec_bfmlal_idx); + return; } g_assert_not_reached(); case 0x11: /* FCMLA #0 */ |