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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-04-30 14:27:34 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-05-10 13:24:09 +0100 |
| commit | 4a800a739d6c7760a35b4be6a01bb3819de51030 (patch) | |
| tree | 0a134840db9538269933c157b6b5bbaba26082a7 /target/arm/translate-a32.h | |
| parent | 06085d6a10e11fb9df871648668b072905936566 (diff) | |
| download | qemu-4a800a739d6c7760a35b4be6a01bb3819de51030.zip qemu-4a800a739d6c7760a35b4be6a01bb3819de51030.tar.gz qemu-4a800a739d6c7760a35b4be6a01bb3819de51030.tar.bz2 | |
target/arm: Make functions used by translate-vfp global
Make the remaining functions which are needed by translate-vfp.c.inc
global.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210430132740.10391-8-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-a32.h')
| -rw-r--r-- | target/arm/translate-a32.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 522aa83..326cbaf 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -30,6 +30,13 @@ void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop); +TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); +void gen_set_cpsr(TCGv_i32 var, uint32_t mask); +void gen_set_condexec(DisasContext *s); +void gen_set_pc_im(DisasContext *s, target_ulong val); +void gen_lookup_tb(DisasContext *s); +long vfp_reg_offset(bool dp, unsigned reg); +long neon_full_reg_offset(unsigned reg); static inline TCGv_i32 load_cpu_offset(int offset) { @@ -57,6 +64,8 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } +void store_reg(DisasContext *s, int reg, TCGv_i32 var); + void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, int index, MemOp opc); void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, @@ -110,4 +119,13 @@ DO_GEN_ST(32, MO_UL) #undef DO_GEN_LD #undef DO_GEN_ST +#if defined(CONFIG_USER_ONLY) +#define IS_USER(s) 1 +#else +#define IS_USER(s) (s->user) +#endif + +/* Set NZCV flags from the high 4 bits of var. */ +#define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) + #endif |