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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-05-18 06:08:30 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-18 06:08:30 -0700 |
| commit | 266ccbb27b3ec6661f22395ec2c41d854c94d761 (patch) | |
| tree | 72ed207c2243e335d6919dfb167d206dea733b40 /target/arm/tcg/meson.build | |
| parent | d27e7c359330ba7020bdbed7ed2316cb4cf6ffc1 (diff) | |
| parent | 91608e2a44f36e79cb83f863b8a7bb57d2c98061 (diff) | |
| download | qemu-266ccbb27b3ec6661f22395ec2c41d854c94d761.zip qemu-266ccbb27b3ec6661f22395ec2c41d854c94d761.tar.gz qemu-266ccbb27b3ec6661f22395ec2c41d854c94d761.tar.bz2 | |
Merge tag 'pull-target-arm-20230518' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix vd == vm overlap in sve_ldff1_z
* Add support for MTE with KVM guests
* Add RAZ/WI handling for DBGDTR[TX|RX]
* Start of conversion of A64 decoder to decodetree
* Saturate L2CTLR_EL1 core count field rather than overflowing
* vexpress: Avoid trivial memory leak of 'flashalias'
* sbsa-ref: switch default cpu core to Neoverse-N1
* sbsa-ref: use Bochs graphics card instead of VGA
* MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list
* docs: Convert u2f.txt to rST
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# gpg: Signature made Thu 18 May 2023 05:49:55 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20230518' of https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits)
docs: Convert u2f.txt to rST
hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'
target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing
target/arm: Convert ERET, ERETAA, ERETAB to decodetree
target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree
target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree
target/arm: Convert BR, BLR, RET to decodetree
target/arm: Convert conditional branch insns to decodetree
target/arm: Convert TBZ, TBNZ to decodetree
target/arm: Convert CBZ, CBNZ to decodetree
target/arm: Convert unconditional branch immediate to decodetree
target/arm: Convert Extract instructions to decodetree
target/arm: Convert Bitfield to decodetree
target/arm: Convert Move wide (immediate) to decodetree
target/arm: Convert Logical (immediate) to decodetree
target/arm: Replace bitmask64 with MAKE_64BIT_MASK
target/arm: Convert Add/subtract (immediate with tags) to decodetree
target/arm: Convert Add/subtract (immediate) to decodetree
target/arm: Split gen_add_CC and gen_sub_CC
target/arm: Convert PC-rel addressing to decodetree
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/tcg/meson.build')
| -rw-r--r-- | target/arm/tcg/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 4d99f6d..130ed62 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -13,6 +13,7 @@ gen = [ decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), + decodetree.process('a64.decode', extra_args: ['--static-decode=disas_a64']), ] arm_ss.add(gen) |