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authorRichard Henderson <richard.henderson@linaro.org>2019-09-04 12:30:18 -0700
committerPeter Maydell <peter.maydell@linaro.org>2019-09-05 13:23:03 +0100
commitc5c426d4c680f908a1e262091a17b088b5709200 (patch)
tree4c7dcbf6447132cade0354305b886046186ce7ef /target/arm/t32.decode
parent8f4451274b7010c1f50e0baa5bb608f19f02b90f (diff)
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target/arm: Convert LDM, STM
This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t32.decode')
-rw-r--r--target/arm/t32.decode10
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index f315fde..f1e2b93 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -37,6 +37,7 @@
&mrs_bank !extern rd r sysm
&ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm
+&ldst_block !extern rn i b u w list
&strex !extern rn rd rt rt2 imm
&ldrex !extern rn rt rt2 imm
&bfx !extern rd rn lsb widthm1
@@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot
UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot
SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot
UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot
+
+# Load/store multiple
+
+@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block u=0
+
+STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0
+STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
+LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
+LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1