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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-08 20:45:24 +0530 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-07-11 13:43:51 +0100 |
| commit | 7dbfafc157290b52af6109b82b8398d10ef5c3b3 (patch) | |
| tree | e74929c5054c72d53d8cb33df5a338b122d4cc38 /target/arm/sve.decode | |
| parent | 598ab0b24c0cb807b3f380ab422915dd6c229026 (diff) | |
| download | qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.zip qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.gz qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.bz2 | |
target/arm: Implement REVD
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 966803c..a9e48f0 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -652,6 +652,7 @@ REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn +REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 # SVE vector splice (predicated, destructive) SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm |