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authorPeter Maydell <peter.maydell@linaro.org>2021-06-17 13:15:54 +0100
committerPeter Maydell <peter.maydell@linaro.org>2021-06-21 17:12:50 +0100
commitab59362fca0c23fbd21daceb78d6b2966fbf9793 (patch)
tree02154d0f82e9f8b5a778763c3d83f4bb351b5cad /target/arm/mve_helper.c
parent614dd4f3ba2a025eae5235c3466ef6da191879f6 (diff)
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target/arm: Implement MVE VDUP
Implement the MVE VDUP insn, which duplicates a value from a general-purpose register into every lane of a vector register (subject to predication). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-11-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/mve_helper.c')
-rw-r--r--target/arm/mve_helper.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 7b662f9..e17ffdc 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -246,6 +246,22 @@ static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask)
uint64_t *: mergemask_uq, \
int64_t *: mergemask_sq)(D, R, M)
+void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val)
+{
+ /*
+ * The generated code already replicated an 8 or 16 bit constant
+ * into the 32-bit value, so we only need to write the 32-bit
+ * value to all elements of the Qreg, allowing for predication.
+ */
+ uint32_t *d = vd;
+ uint16_t mask = mve_element_mask(env);
+ unsigned e;
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
+ mergemask(&d[H4(e)], val, mask);
+ }
+ mve_advance_vpt(env);
+}
+
#define DO_1OP(OP, ESIZE, TYPE, FN) \
void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
{ \