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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-08-13 17:11:55 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-08-25 10:48:50 +0100 |
| commit | 1241f148d52eea7c9350df918da0eafdfc539327 (patch) | |
| tree | c982b3e6f2e512a89a48ef16356bc9cca553b7e0 /target/arm/mve.decode | |
| parent | d5c571ea6d1558934b0d1a95c51a2c084cf4fd85 (diff) | |
| download | qemu-1241f148d52eea7c9350df918da0eafdfc539327.zip qemu-1241f148d52eea7c9350df918da0eafdfc539327.tar.gz qemu-1241f148d52eea7c9350df918da0eafdfc539327.tar.bz2 | |
target/arm: Implement MVE VMOV to/from 2 general-purpose registers
Implement the MVE VMOV forms that move data between 2 general-purpose
registers and 2 32-bit lanes in a vector register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/mve.decode')
| -rw-r--r-- | target/arm/mve.decode | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 0955ed0..774ee2a 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -136,6 +136,10 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ size=2 p=1 +# Moves between 2 32-bit vector lanes and 2 general purpose registers +VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd +VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd + # Vector 2-op VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |