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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-06-28 14:58:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-02 11:48:37 +0100 |
| commit | 2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664 (patch) | |
| tree | 2dd1dcfffacdb9b8d48b2374c6fe10dd69d83772 /target/arm/mve.decode | |
| parent | d6f9e011e8643fb00303e3fec24dd1e424f3f5b3 (diff) | |
| download | qemu-2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664.zip qemu-2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664.tar.gz qemu-2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664.tar.bz2 | |
target/arm: Implement MVE VSHLC
Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/mve.decode')
| -rw-r--r-- | target/arm/mve.decode | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 1d11387..914b108 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -419,3 +419,5 @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h + +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd |