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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:47 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:36 +0000 |
| commit | f4ecc01537684a4125c35433f3097295d0a1f839 (patch) | |
| tree | ef4829b288da0e4c5332e58e34b95f4adcb4b33a /target/arm/internals.h | |
| parent | d06449f2eb555896057ee047b3009a3616d52028 (diff) | |
| download | qemu-f4ecc01537684a4125c35433f3097295d0a1f839.zip qemu-f4ecc01537684a4125c35433f3097295d0a1f839.tar.gz qemu-f4ecc01537684a4125c35433f3097295d0a1f839.tar.bz2 | |
target/arm: Honor TCR_ELx.{I}PS
This field controls the output (intermediate) physical address size
of the translation process. V8 requires to raise an AddressSize
fault if the page tables are programmed incorrectly, such that any
intermediate descriptor address, or the final translated address,
is out of range.
Add a PS field to ARMVAParameters, and properly compute outputsize
in get_phys_addr_lpae. Test the descaddr as extracted from TTBR
and from page table entries.
Restrict descaddrmask so that we won't raise the fault for v7.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index fefd1fb..3d3d41b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,6 +1032,7 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) */ typedef struct ARMVAParameters { unsigned tsz : 8; + unsigned ps : 3; unsigned select : 1; bool tbi : 1; bool epd : 1; |