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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2022-03-16 17:46:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-18 11:19:19 +0000 |
| commit | 4a7319b750d2a465c9697fb0c72584c5d4e9073a (patch) | |
| tree | ce11757a63cdccb46d2ba8f99e59b4a64dc8d887 /target/arm/helper.c | |
| parent | c28d4b8656c836b5b166b35e4c48ff26d9405b59 (diff) | |
| download | qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.zip qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.gz qemu-4a7319b750d2a465c9697fb0c72584c5d4e9073a.tar.bz2 | |
target/arm: Make rvbar settable after realize
Make the rvbar property settable after realize. This is done
in preparation to model the ZynqMP's runtime configurable rvbar.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index b5c8caa..812ca59 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7967,7 +7967,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8011,7 +8012,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo rvbar = { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar + .access = PL2_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }; define_one_arm_cp_reg(cpu, &rvbar); } @@ -8048,7 +8050,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo el3_regs[] = { { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, + .access = PL3_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, |