diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-20 10:51:49 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-27 11:18:17 +0100 |
| commit | c37e6ac9eb94667d803d0cc1c4cc39ab351a6921 (patch) | |
| tree | e579e3bf77ddda583a7f28a52457421dcd2e761f /target/arm/helper.c | |
| parent | bca063d579cbd6075d0bab78cc702131df199d6e (diff) | |
| download | qemu-c37e6ac9eb94667d803d0cc1c4cc39ab351a6921.zip qemu-c37e6ac9eb94667d803d0cc1c4cc39ab351a6921.tar.gz qemu-c37e6ac9eb94667d803d0cc1c4cc39ab351a6921.tar.bz2 | |
target/arm: Add SVCR
This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220620175235.60881-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c080c6..3acc1dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6349,11 +6349,24 @@ static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= R_SVCR_SM_MASK | R_SVCR_ZA_MASK; + /* TODO: Side effects. */ + env->svcr = value; +} + static const ARMCPRegInfo sme_reginfo[] = { { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, .access = PL0_RW, .accessfn = access_tpidr2, .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, + { .name = "SVCR", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, + .access = PL0_RW, .type = ARM_CP_SME, + .fieldoffset = offsetof(CPUARMState, svcr), + .writefn = svcr_write, .raw_writefn = raw_write }, }; #endif /* TARGET_AARCH64 */ |