diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-10 14:32:35 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-10 14:32:35 +0100 |
| commit | 6bcbb07af6a601b2521b07a639861218fbf0c87e (patch) | |
| tree | 881383c71e65e37dda854b617a91c98b6138172b /target/arm/helper.c | |
| parent | bfe43e3d14687f2149451f278671c2c552d96b0a (diff) | |
| download | qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.zip qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.tar.gz qemu-6bcbb07af6a601b2521b07a639861218fbf0c87e.tar.bz2 | |
target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
Since DDI0487F.a, the RW bit is RAO/WI. When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index ff9f9fe..6457e63 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1747,6 +1747,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) value |= SCR_FW | SCR_AW; /* RES1 */ valid_mask &= ~SCR_NET; /* RES0 */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu) && + !cpu_isar_feature(aa64_aa32_el2, cpu)) { + value |= SCR_RW; /* RAO/WI */ + } if (cpu_isar_feature(aa64_ras, cpu)) { valid_mask |= SCR_TERR; } |