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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-06-08 19:38:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-06-08 19:38:59 +0100 |
| commit | 414c54d515dba16bfaef643a8acec200c05f229a (patch) | |
| tree | 7e67548bc1de794e33dbee7ae802b23f3f953b5c /target/arm/helper.c | |
| parent | f305bf9436896b4cd9ef622034e166b024780874 (diff) | |
| download | qemu-414c54d515dba16bfaef643a8acec200c05f229a.zip qemu-414c54d515dba16bfaef643a8acec200c05f229a.tar.gz qemu-414c54d515dba16bfaef643a8acec200c05f229a.tar.bz2 | |
target/arm: Add ID_AA64SMFR0_EL1
This register is allocated from the existing block of id registers,
so it is already RES0 for cpus that do not implement SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 400f7cd..ac9942d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7722,11 +7722,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64zfr0 }, - { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64smfr0 }, { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST, |