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authorPeter Maydell <peter.maydell@linaro.org>2018-05-31 14:50:51 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-05-31 14:50:51 +0100
commit2cfbf36ec07f7cac1aabb3b86f1c95c8a55424ba (patch)
tree9a2dd2594d751d43234a46d92ebac703cdbf2e1c /target/arm/helper-a64.c
parenta3ac12fba028df90f7b3dbec924995c126c41022 (diff)
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target/arm: Honour FPCR.FZ in FRECPX
The FRECPX instructions should (like most other floating point operations) honour the FPCR.FZ bit which specifies whether input denormals should be flushed to zero (or FZ16 for the half-precision version). We forgot to implement this, which doesn't affect the results (since the calculation doesn't actually care about the mantissa bits) but did mean we were failing to set the FPSR.IDC bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/helper-a64.c')
-rw-r--r--target/arm/helper-a64.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index f92bdea..c4d2a04 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -384,6 +384,8 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
return nan;
}
+ a = float16_squash_input_denormal(a, fpst);
+
val16 = float16_val(a);
sbit = 0x8000 & val16;
exp = extract32(val16, 10, 5);
@@ -413,6 +415,8 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
return nan;
}
+ a = float32_squash_input_denormal(a, fpst);
+
val32 = float32_val(a);
sbit = 0x80000000ULL & val32;
exp = extract32(val32, 23, 8);
@@ -442,6 +446,8 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
return nan;
}
+ a = float64_squash_input_denormal(a, fpst);
+
val64 = float64_val(a);
sbit = 0x8000000000000000ULL & val64;
exp = extract64(float64_val(a), 52, 11);