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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-06-23 11:15:45 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-06-23 11:15:45 +0100 |
| commit | bb5cc2c860c4d359e107ede2464dfe5cd297f16b (patch) | |
| tree | c46d173ac851d7d8a72f9d6a15cf04c4afdea3b0 /target/arm/cpu.h | |
| parent | d38fa9670d14331fc766dfc15b2bc6628d0149d0 (diff) | |
| download | qemu-bb5cc2c860c4d359e107ede2464dfe5cd297f16b.zip qemu-bb5cc2c860c4d359e107ede2464dfe5cd297f16b.tar.gz qemu-bb5cc2c860c4d359e107ede2464dfe5cd297f16b.tar.bz2 | |
target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b338619..590216b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2870,8 +2870,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A, /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -2935,6 +2937,23 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + /* Assert the relative order of the physical mmu indexes. */ + QEMU_BUILD_BUG_ON(ARMSS_Secure != 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm); + + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and |