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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-05 16:09:16 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-05 16:09:16 +0000 |
| commit | d1fb4da208411ce7b3dafb9f9e7726ebcec14edb (patch) | |
| tree | 9dec3008535ba72565c501fc64499e5e8e4a0be6 /target/arm/cpu.h | |
| parent | f4228077e80cb30811e185d5330d2df778e667b3 (diff) | |
| download | qemu-d1fb4da208411ce7b3dafb9f9e7726ebcec14edb.zip qemu-d1fb4da208411ce7b3dafb9f9e7726ebcec14edb.tar.gz qemu-d1fb4da208411ce7b3dafb9f9e7726ebcec14edb.tar.bz2 | |
target/arm: Improve masking of HCR/HCR2 RES0 bits
Don't merely start with v8.0, handle v7VE as well. Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
0 files changed, 0 insertions, 0 deletions