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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-02-28 10:55:16 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-02-28 11:03:04 +0000 |
| commit | 602f6e42cfbfe9278be34e9b91d2ceb695837e02 (patch) | |
| tree | fab04e997914a2856797c661155179c0d8ad0155 /target/arm/cpu.c | |
| parent | aab7a3786f085cb4c6842c3c8ea0c86e2c835248 (diff) | |
| download | qemu-602f6e42cfbfe9278be34e9b91d2ceb695837e02.zip qemu-602f6e42cfbfe9278be34e9b91d2ceb695837e02.tar.gz qemu-602f6e42cfbfe9278be34e9b91d2ceb695837e02.tar.bz2 | |
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.
This change doesn't alter behaviour for any of our CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4d7f6a3..a3baf4e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1014,7 +1014,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); - set_feature(env, ARM_FEATURE_VFP_FP16); } if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); @@ -1675,7 +1674,6 @@ static void cortex_a9_initfn(Object *obj) cpu->dtb_compatible = "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); - set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); |