diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-02-24 14:22:24 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-28 16:14:57 +0000 |
| commit | c52881bbc22b50db99a6c37171ad3eea7d959ae6 (patch) | |
| tree | 5fee296b9c6e8422f19bb2182d88401ce338f768 /target/arm/cpu.c | |
| parent | 82f6abe16b9b951180657c5fe15942d5214aa12e (diff) | |
| download | qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.zip qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.tar.gz qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.tar.bz2 | |
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.c')
| -rw-r--r-- | target/arm/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5be4c25..dc45865 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1512,7 +1512,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) u = FIELD_DP32(u, MVFR1, SIMDINT, 0); u = FIELD_DP32(u, MVFR1, SIMDSP, 0); u = FIELD_DP32(u, MVFR1, SIMDHP, 0); - u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); cpu->isar.mvfr1 = u; u = cpu->isar.mvfr2; @@ -1535,6 +1534,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) u = cpu->isar.mvfr0; u = FIELD_DP32(u, MVFR0, SIMDREG, 0); cpu->isar.mvfr0 = u; + + /* Despite the name, this field covers both VFP and Neon */ + u = cpu->isar.mvfr1; + u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 = u; } if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { |