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| author | Anup Patel <apatel@ventanamicro.com> | 2023-01-20 18:29:48 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:22 +1000 |
| commit | 14cb78bfaf4f99283252d9683ea4c0d97274ddea (patch) | |
| tree | 1a12aa4f23feeec202270960e121e8f5a03119c5 /target/arm/cpregs.h | |
| parent | 2cfb3b6c9b78fd9d47a2934ba53293c73c680406 (diff) | |
| download | qemu-14cb78bfaf4f99283252d9683ea4c0d97274ddea.zip qemu-14cb78bfaf4f99283252d9683ea4c0d97274ddea.tar.gz qemu-14cb78bfaf4f99283252d9683ea4c0d97274ddea.tar.bz2 | |
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/arm/cpregs.h')
0 files changed, 0 insertions, 0 deletions