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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2017-07-18 01:55:39 -0300 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-07-19 14:45:16 -0700 |
| commit | 729028a6e2816d64cb01cf4c1920686be90600da (patch) | |
| tree | ff362b7afcddcc75ea25b8287b4603e9dce5fe3e /target/alpha/translate.c | |
| parent | 08d64e0db02e826b063d2b0d8b84f1cb1f7306c9 (diff) | |
| download | qemu-729028a6e2816d64cb01cf4c1920686be90600da.zip qemu-729028a6e2816d64cb01cf4c1920686be90600da.tar.gz qemu-729028a6e2816d64cb01cf4c1920686be90600da.tar.bz2 | |
target/alpha: optimize gen_cvtlq() using deposit op
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/alpha/translate.c')
| -rw-r--r-- | target/alpha/translate.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 90e6d52..744d8bb 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -783,11 +783,9 @@ static void gen_cvtlq(TCGv vc, TCGv vb) /* The arithmetic right shift here, plus the sign-extended mask below yields a sign-extended result without an explicit ext32s_i64. */ - tcg_gen_sari_i64(tmp, vb, 32); - tcg_gen_shri_i64(vc, vb, 29); - tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000); - tcg_gen_andi_i64(vc, vc, 0x3fffffff); - tcg_gen_or_i64(vc, vc, tmp); + tcg_gen_shri_i64(tmp, vb, 29); + tcg_gen_sari_i64(vc, vb, 32); + tcg_gen_deposit_i64(vc, vc, tmp, 0, 30); tcg_temp_free(tmp); } |