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author | Claudio Fontana <cfontana@suse.de> | 2021-02-04 17:39:23 +0100 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:15 -1000 |
commit | 78271684719f34c1cc19f895e089f2f19b69698d (patch) | |
tree | 5f47406eb8c2be4e37e411e5053678e4d91e09d3 /target/alpha/cpu.c | |
parent | c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d (diff) | |
download | qemu-78271684719f34c1cc19f895e089f2f19b69698d.zip qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.gz qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.bz2 |
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/alpha/cpu.c')
-rw-r--r-- | target/alpha/cpu.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 0710298..27192b6 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,20 @@ static void alpha_cpu_initfn(Object *obj) #endif } +#include "hw/core/tcg-cpu-ops.h" + +static struct TCGCPUOps alpha_tcg_ops = { + .initialize = alpha_translate_init, + .cpu_exec_interrupt = alpha_cpu_exec_interrupt, + .tlb_fill = alpha_cpu_tlb_fill, + +#ifndef CONFIG_USER_ONLY + .do_interrupt = alpha_cpu_do_interrupt, + .do_transaction_failed = alpha_cpu_do_transaction_failed, + .do_unaligned_access = alpha_cpu_do_unaligned_access, +#endif /* !CONFIG_USER_ONLY */ +}; + static void alpha_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -217,22 +231,17 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; - cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt; - cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; cc->gdb_write_register = alpha_cpu_gdb_write_register; - cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed; - cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access; cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; dc->vmsd = &vmstate_alpha_cpu; #endif cc->disas_set_info = alpha_cpu_disas_set_info; - cc->tcg_ops.initialize = alpha_translate_init; + cc->tcg_ops = &alpha_tcg_ops; cc->gdb_num_core_regs = 67; } |