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| author | Alexander Graf <agraf@suse.de> | 2013-12-17 19:42:33 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:33 +0000 |
| commit | b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c (patch) | |
| tree | 23f6ef2615c1ad87282d9caedcea85ab6cae1e75 /target-xtensa | |
| parent | 11e169de9940b9dc057e534ecf864c542fafb425 (diff) | |
| download | qemu-b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c.zip qemu-b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c.tar.gz qemu-b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c.tar.bz2 | |
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: reimplemented on top of new decoder structure]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-xtensa')
0 files changed, 0 insertions, 0 deletions