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author | Max Filippov <jcmvbkbc@gmail.com> | 2012-12-05 07:15:20 +0400 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 18:48:26 +0000 |
commit | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 (patch) | |
tree | bbd6697bd198b45b2322e5b43d3ab5159e093d98 /target-xtensa/overlay_tool.h | |
parent | 536b558f5896ebbd635b57fa393e82faaa32ad52 (diff) | |
download | qemu-fcc803d119a4c01a9b0ee5bda35fda1eeabffa33.zip qemu-fcc803d119a4c01a9b0ee5bda35fda1eeabffa33.tar.gz qemu-fcc803d119a4c01a9b0ee5bda35fda1eeabffa33.tar.bz2 |
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-xtensa/overlay_tool.h')
-rw-r--r-- | target-xtensa/overlay_tool.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h index e395053..50bf573 100644 --- a/target-xtensa/overlay_tool.h +++ b/target-xtensa/overlay_tool.h @@ -42,6 +42,10 @@ #define XCHAL_VECBASE_RESET_VADDR 0 #endif +#ifndef XCHAL_HW_MIN_VERSION +#define XCHAL_HW_MIN_VERSION 0 +#endif + #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) #define XTENSA_OPTIONS ( \ @@ -62,6 +66,8 @@ XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ + XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \ + XTENSA_OPTION_ATOMCTL) | \ /* Interrupts and exceptions */ \ XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \ |