diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-06-28 23:18:47 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-26 23:23:54 +0200 |
| commit | a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34 (patch) | |
| tree | 0a87f5f9ab3ff51ef996c69ded7cfa8f97768e92 /target-xtensa/cpu.c | |
| parent | 19a77215f1ba966c4d37dadec45f38be789b8529 (diff) | |
| download | qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.zip qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.gz qemu-a0e372f0c49ac01faeaeb73a6e8f50e8ac615f34.tar.bz2 | |
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.
CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-xtensa/cpu.c')
| -rw-r--r-- | target-xtensa/cpu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 5a39971..560fa0c 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -85,8 +85,11 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) { + CPUState *cs = CPU(dev); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); + cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; + xcc->parent_realize(dev, errp); } |