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| author | Richard Henderson <rth@twiddle.net> | 2015-08-21 11:57:42 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2015-09-15 07:45:33 -0700 |
| commit | 73c543776b6983178026f744d3579ae16ae9b5b2 (patch) | |
| tree | bc1dcc9daa913c9e71964eafeeeaf4a74b5279a9 /target-tilegx/translate.c | |
| parent | e04e98bf277309c3964cfd773c0d4c0428f64399 (diff) | |
| download | qemu-73c543776b6983178026f744d3579ae16ae9b5b2.zip qemu-73c543776b6983178026f744d3579ae16ae9b5b2.tar.gz qemu-73c543776b6983178026f744d3579ae16ae9b5b2.tar.bz2 | |
target-tilegx: Handle comparison instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-tilegx/translate.c')
| -rw-r--r-- | target-tilegx/translate.c | 39 |
1 files changed, 33 insertions, 6 deletions
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 9c95633..f2dd824 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -473,32 +473,52 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(CMOVEQZ, 4, Y0): case OE_RRR(CMOVNEZ, 0, X0): case OE_RRR(CMOVNEZ, 4, Y0): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(CMPEQ, 0, X0): case OE_RRR(CMPEQ, 0, X1): case OE_RRR(CMPEQ, 3, Y0): case OE_RRR(CMPEQ, 3, Y1): + tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb); + mnemonic = "cmpeq"; + break; case OE_RRR(CMPEXCH4, 0, X1): case OE_RRR(CMPEXCH, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(CMPLES, 0, X0): case OE_RRR(CMPLES, 0, X1): case OE_RRR(CMPLES, 2, Y0): case OE_RRR(CMPLES, 2, Y1): + tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb); + mnemonic = "cmples"; + break; case OE_RRR(CMPLEU, 0, X0): case OE_RRR(CMPLEU, 0, X1): case OE_RRR(CMPLEU, 2, Y0): case OE_RRR(CMPLEU, 2, Y1): + tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb); + mnemonic = "cmpleu"; + break; case OE_RRR(CMPLTS, 0, X0): case OE_RRR(CMPLTS, 0, X1): case OE_RRR(CMPLTS, 2, Y0): case OE_RRR(CMPLTS, 2, Y1): + tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb); + mnemonic = "cmplts"; + break; case OE_RRR(CMPLTU, 0, X0): case OE_RRR(CMPLTU, 0, X1): case OE_RRR(CMPLTU, 2, Y0): case OE_RRR(CMPLTU, 2, Y1): + tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb); + mnemonic = "cmpltu"; + break; case OE_RRR(CMPNE, 0, X0): case OE_RRR(CMPNE, 0, X1): case OE_RRR(CMPNE, 3, Y0): case OE_RRR(CMPNE, 3, Y1): + tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb); + mnemonic = "cmpne"; + break; case OE_RRR(CMULAF, 0, X0): case OE_RRR(CMULA, 0, X0): case OE_RRR(CMULFR, 0, X0): @@ -886,13 +906,25 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, tcg_gen_andi_tl(tdest, tsrca, imm); mnemonic = "andi"; break; + case OE(CMPEQI_OPCODE_Y0, 0, Y0): + case OE(CMPEQI_OPCODE_Y1, 0, Y1): case OE_IM(CMPEQI, X0): case OE_IM(CMPEQI, X1): + tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm); + mnemonic = "cmpeqi"; + break; + case OE(CMPLTSI_OPCODE_Y0, 0, Y0): + case OE(CMPLTSI_OPCODE_Y1, 0, Y1): case OE_IM(CMPLTSI, X0): case OE_IM(CMPLTSI, X1): + tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm); + mnemonic = "cmpltsi"; + break; case OE_IM(CMPLTUI, X0): case OE_IM(CMPLTUI, X1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm); + mnemonic = "cmpltui"; + break; case OE_IM(LD1S_ADD, X1): memop = MO_SB; mnemonic = "ld1s_add"; @@ -1042,11 +1074,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext, tcg_gen_ext32s_tl(tdest, tdest); mnemonic = "addxli"; break; - case OE(CMPEQI_OPCODE_Y0, 0, Y0): - case OE(CMPEQI_OPCODE_Y1, 0, Y1): - case OE(CMPLTSI_OPCODE_Y0, 0, Y0): - case OE(CMPLTSI_OPCODE_Y1, 0, Y1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE(SHL16INSLI_OPCODE_X0, 0, X0): case OE(SHL16INSLI_OPCODE_X1, 0, X1): tcg_gen_shli_tl(tdest, tsrca, 16); |