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authorBlue Swirl <blauwirbel@gmail.com>2009-08-15 16:52:54 +0000
committerBlue Swirl <blauwirbel@gmail.com>2009-08-15 16:52:54 +0000
commitcfa90513a3d41a033aa3bacd5396b81edb0f9ebf (patch)
treee374da050326d5e18fbf6bede2287e4de3132b8a /target-sparc
parent802670e6c9026c945c232a46bb5c789601334280 (diff)
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Fix desynchronization of condition code state when a memory access traps
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/translate.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5ef543a..9bbfd3c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -912,6 +912,11 @@ static inline void save_npc(DisasContext *dc, TCGv cond)
static inline void save_state(DisasContext *dc, TCGv cond)
{
tcg_gen_movi_tl(cpu_pc, dc->pc);
+ /* flush pending conditional evaluations before exposing cpu state */
+ if (dc->cc_op != CC_OP_FLAGS) {
+ dc->cc_op = CC_OP_FLAGS;
+ gen_helper_compute_psr();
+ }
save_npc(dc, cond);
}
@@ -4110,6 +4115,12 @@ static void disas_sparc_insn(DisasContext * dc)
{
unsigned int xop = GET_FIELD(insn, 7, 12);
+ /* flush pending conditional evaluations before exposing
+ cpu state */
+ if (dc->cc_op != CC_OP_FLAGS) {
+ dc->cc_op = CC_OP_FLAGS;
+ gen_helper_compute_psr();
+ }
cpu_src1 = get_src1(insn, cpu_src1);
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
rs2 = GET_FIELD(insn, 27, 31);