aboutsummaryrefslogtreecommitdiff
path: root/target-sparc
diff options
context:
space:
mode:
authorIgor V. Kovalenko <igor.v.kovalenko@gmail.com>2010-06-02 23:38:45 +0400
committerBlue Swirl <blauwirbel@gmail.com>2010-06-02 20:03:52 +0000
commit1295001c53fe816776bae810bed0a653ea0c6475 (patch)
treea2bbf88d78829768db12818888bf99fbbbc90060 /target-sparc
parent9168b3a545fae3db8ad0ee7de872c4302651ba7f (diff)
downloadqemu-1295001c53fe816776bae810bed0a653ea0c6475.zip
qemu-1295001c53fe816776bae810bed0a653ea0c6475.tar.gz
qemu-1295001c53fe816776bae810bed0a653ea0c6475.tar.bz2
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns - address masking for lddf and stdf insns - address masking for translating ASI (Ultrasparc IIi) v0->v1: - move arch-specific code to helpers and drop more ifdefs at call sites using new helper asi_address_mask() - change user emulation to use asi_address_mask() Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/op_helper.c50
-rw-r--r--target-sparc/translate.c4
2 files changed, 52 insertions, 2 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index ef3504f..f5e4633 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -247,6 +247,42 @@ static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
return addr;
}
+/* returns true if access using this ASI is to have address translated by MMU
+ otherwise access is to raw physical address */
+static inline int is_translating_asi(int asi)
+{
+#ifdef TARGET_SPARC64
+ /* Ultrasparc IIi translating asi
+ - note this list is defined by cpu implementation
+ */
+ switch (asi) {
+ case 0x04 ... 0x11:
+ case 0x18 ... 0x19:
+ case 0x24 ... 0x2C:
+ case 0x70 ... 0x73:
+ case 0x78 ... 0x79:
+ case 0x80 ... 0xFF:
+ return 1;
+
+ default:
+ return 0;
+ }
+#else
+ /* TODO: check sparc32 bits */
+ return 0;
+#endif
+}
+
+static inline target_ulong asi_address_mask(CPUState *env1,
+ int asi, target_ulong addr)
+{
+ if (is_translating_asi(asi)) {
+ return address_mask(env, addr);
+ } else {
+ return addr;
+ }
+}
+
static void raise_exception(int tt)
{
env->exception_index = tt;
@@ -2151,7 +2187,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
- addr = address_mask(env, addr);
+ addr = asi_address_mask(env, asi, addr);
switch (asi) {
case 0x82: // Primary no-fault
@@ -2254,7 +2290,7 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
- addr = address_mask(env, addr);
+ addr = asi_address_mask(env, asi, addr);
/* Convert to little endian */
switch (asi) {
@@ -2331,6 +2367,8 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0x82: // Primary no-fault
case 0x8a: // Primary no-fault LE
@@ -2682,6 +2720,8 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
raise_exception(TT_PRIV_ACT);
helper_check_align(addr, size - 1);
+ addr = asi_address_mask(env, asi, addr);
+
/* Convert to little endian */
switch (asi) {
case 0x0c: // Nucleus Little Endian (LE)
@@ -3056,6 +3096,8 @@ void helper_ldda_asi(target_ulong addr, int asi, int rd)
&& !(env->hpstate & HS_PRIV)))
raise_exception(TT_PRIV_ACT);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
#if !defined(CONFIG_USER_ONLY)
case 0x24: // Nucleus quad LDD 128 bit atomic
@@ -3103,6 +3145,8 @@ void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
target_ulong val;
helper_check_align(addr, 3);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0xf0: // Block load primary
case 0xf1: // Block load secondary
@@ -3145,6 +3189,8 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
target_ulong val = 0;
helper_check_align(addr, 3);
+ addr = asi_address_mask(env, asi, addr);
+
switch (asi) {
case 0xe0: // UA2007 Block commit store primary (cache flush)
case 0xe1: // UA2007 Block commit store secondary (cache flush)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 72ca0b4..eff64d4 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4490,6 +4490,7 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, FLOAT128);
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_ldqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
@@ -4500,6 +4501,7 @@ static void disas_sparc_insn(DisasContext * dc)
TCGv_i32 r_const;
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_lddf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_DT0_fpr(DFPREG(rd));
@@ -4635,6 +4637,7 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_op_load_fpr_QT0(QFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stqf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}
@@ -4657,6 +4660,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_load_fpr_DT0(DFPREG(rd));
r_const = tcg_const_i32(dc->mem_idx);
+ gen_address_mask(dc, cpu_addr);
gen_helper_stdf(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
}