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| author | Richard Henderson <rth@twiddle.net> | 2011-10-18 09:24:43 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2011-10-26 14:00:19 -0700 |
| commit | 793a137a41ad4125011c7022cf16a1baa40a5ab6 (patch) | |
| tree | 10b81a781533fb487d02e67b3cd9aae23f6c1a39 /target-sparc | |
| parent | add545ab11450c7049468fccdcd362b47740d9fe (diff) | |
| download | qemu-793a137a41ad4125011c7022cf16a1baa40a5ab6.zip qemu-793a137a41ad4125011c7022cf16a1baa40a5ab6.tar.gz qemu-793a137a41ad4125011c7022cf16a1baa40a5ab6.tar.bz2 | |
target-sparc: Implement BMASK/BSHUFFLE.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-sparc')
| -rw-r--r-- | target-sparc/helper.h | 1 | ||||
| -rw-r--r-- | target-sparc/translate.c | 14 | ||||
| -rw-r--r-- | target-sparc/vis_helper.c | 29 |
3 files changed, 40 insertions, 4 deletions
diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 73fb0ee..3ee12a9 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -140,6 +140,7 @@ DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) +DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) #define VIS_HELPER(name) \ DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE, \ i64, i64, i64) \ diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 685a907..50fc587 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4192,8 +4192,13 @@ static void disas_sparc_insn(DisasContext * dc) gen_movl_TN_reg(rd, cpu_dst); break; case 0x019: /* VIS II bmask */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + cpu_src1 = get_src1(insn, cpu_src1); + cpu_src2 = get_src1(insn, cpu_src2); + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); + gen_movl_TN_reg(rd, cpu_dst); + break; case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs1); @@ -4314,8 +4319,9 @@ static void disas_sparc_insn(DisasContext * dc) gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); break; case 0x04c: /* VIS II bshuffle */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); + break; case 0x04d: /* VIS I fexpand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 40adb47..7830120 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -470,3 +470,32 @@ uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2) return ret; } + +uint64 helper_bshuffle(uint64_t gsr, uint64_t src1, uint64_t src2) +{ + union { + uint64_t ll[2]; + uint8_t b[16]; + } s; + VIS64 r; + uint32_t i, mask, host; + + /* Set up S such that we can index across all of the bytes. */ +#ifdef HOST_WORDS_BIGENDIAN + s.ll[0] = src1; + s.ll[1] = src2; + host = 0; +#else + s.ll[1] = src1; + s.ll[0] = src2; + host = 15; +#endif + mask = gsr >> 32; + + for (i = 0; i < 8; ++i) { + unsigned e = (mask >> (28 - i*4)) & 0xf; + r.VIS_B64(i) = s.b[e ^ host]; + } + + return r.ll; +} |