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| author | Igor V. Kovalenko <igor.v.kovalenko@gmail.com> | 2010-06-02 23:38:45 +0400 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-06-02 20:03:52 +0000 |
| commit | 1295001c53fe816776bae810bed0a653ea0c6475 (patch) | |
| tree | a2bbf88d78829768db12818888bf99fbbbc90060 /target-sparc/translate.c | |
| parent | 9168b3a545fae3db8ad0ee7de872c4302651ba7f (diff) | |
| download | qemu-1295001c53fe816776bae810bed0a653ea0c6475.zip qemu-1295001c53fe816776bae810bed0a653ea0c6475.tar.gz qemu-1295001c53fe816776bae810bed0a653ea0c6475.tar.bz2 | |
sparc64: fix missing address masking v1
- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites
using new helper asi_address_mask()
- change user emulation to use asi_address_mask()
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 72ca0b4..eff64d4 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4490,6 +4490,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_ldqf(cpu_addr, r_const); tcg_temp_free_i32(r_const); gen_op_store_QT0_fpr(QFPREG(rd)); @@ -4500,6 +4501,7 @@ static void disas_sparc_insn(DisasContext * dc) TCGv_i32 r_const; r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_lddf(cpu_addr, r_const); tcg_temp_free_i32(r_const); gen_op_store_DT0_fpr(DFPREG(rd)); @@ -4635,6 +4637,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT0(QFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_stqf(cpu_addr, r_const); tcg_temp_free_i32(r_const); } @@ -4657,6 +4660,7 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); + gen_address_mask(dc, cpu_addr); gen_helper_stdf(cpu_addr, r_const); tcg_temp_free_i32(r_const); } |