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author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-04-27 21:07:38 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-04-27 21:07:38 +0000 |
commit | fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242 (patch) | |
tree | ba55ae7076148e88f174b9ce8928f12551583941 /target-sh4 | |
parent | 66a93e0f47fa9869178008c7bc38d66a7c5e45f4 (diff) | |
download | qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.zip qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.tar.gz qemu-fdf9b3e831e8e6b5ceb2a44c742da7d1ab558242.tar.bz2 |
sh4 target (Samuel Tardieu)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
-rw-r--r-- | target-sh4/cpu.h | 138 | ||||
-rw-r--r-- | target-sh4/exec.h | 75 | ||||
-rw-r--r-- | target-sh4/helper.c | 398 | ||||
-rw-r--r-- | target-sh4/op.c | 882 | ||||
-rw-r--r-- | target-sh4/op_helper.c | 372 | ||||
-rw-r--r-- | target-sh4/op_mem.c | 58 | ||||
-rw-r--r-- | target-sh4/translate.c | 1073 |
7 files changed, 2996 insertions, 0 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h new file mode 100644 index 0000000..d99ff8e --- /dev/null +++ b/target-sh4/cpu.h @@ -0,0 +1,138 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _CPU_SH4_H +#define _CPU_SH4_H + +#include "config.h" + +#define TARGET_LONG_BITS 32 +#define TARGET_HAS_ICE 1 + +#include "cpu-defs.h" + +#define TARGET_PAGE_BITS 12 /* 4k XXXXX */ + +#define SR_MD (1 << 30) +#define SR_RB (1 << 29) +#define SR_BL (1 << 28) +#define SR_FD (1 << 15) +#define SR_M (1 << 9) +#define SR_Q (1 << 8) +#define SR_S (1 << 1) +#define SR_T (1 << 0) + +#define FPSCR_FR (1 << 21) +#define FPSCR_SZ (1 << 20) +#define FPSCR_PR (1 << 19) +#define FPSCR_DN (1 << 18) + +#define DELAY_SLOT (1 << 0) +#define DELAY_SLOT_CONDITIONAL (1 << 1) +/* Those are used in contexts only */ +#define BRANCH (1 << 2) +#define BRANCH_CONDITIONAL (1 << 3) +#define MODE_CHANGE (1 << 4) /* Potential MD|RB change */ +#define BRANCH_EXCEPTION (1 << 5) /* Branch after exception */ + +/* XXXXX The structure could be made more compact */ +typedef struct tlb_t { + uint8_t asid; /* address space identifier */ + uint32_t vpn; /* virtual page number */ + uint8_t v; /* validity */ + uint32_t ppn; /* physical page number */ + uint8_t sz; /* page size */ + uint32_t size; /* cached page size in bytes */ + uint8_t sh; /* share status */ + uint8_t c; /* cacheability */ + uint8_t pr; /* protection key */ + uint8_t d; /* dirty */ + uint8_t wt; /* write through */ + uint8_t sa; /* space attribute (PCMCIA) */ + uint8_t tc; /* timing control */ +} tlb_t; + +#define UTLB_SIZE 64 +#define ITLB_SIZE 4 + +typedef struct CPUSH4State { + uint32_t flags; /* general execution flags */ + uint32_t gregs[24]; /* general registers */ + uint32_t fregs[32]; /* floating point registers */ + uint32_t sr; /* status register */ + uint32_t ssr; /* saved status register */ + uint32_t spc; /* saved program counter */ + uint32_t gbr; /* global base register */ + uint32_t vbr; /* vector base register */ + uint32_t sgr; /* saved global register 15 */ + uint32_t dbr; /* debug base register */ + uint32_t pc; /* program counter */ + uint32_t delayed_pc; /* target of delayed jump */ + uint32_t mach; /* multiply and accumulate high */ + uint32_t macl; /* multiply and accumulate low */ + uint32_t pr; /* procedure register */ + uint32_t fpscr; /* floating point status/control register */ + uint32_t fpul; /* floating point communication register */ + + /* Those belong to the specific unit (SH7750) but are handled here */ + uint32_t mmucr; /* MMU control register */ + uint32_t pteh; /* page table entry high register */ + uint32_t ptel; /* page table entry low register */ + uint32_t ptea; /* page table entry assistance register */ + uint32_t ttb; /* tranlation table base register */ + uint32_t tea; /* TLB exception address register */ + uint32_t tra; /* TRAPA exception register */ + uint32_t expevt; /* exception event register */ + uint32_t intevt; /* interrupt event register */ + + jmp_buf jmp_env; + int user_mode_only; + int interrupt_request; + int exception_index; + CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ + tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ +} CPUSH4State; + +CPUSH4State *cpu_sh4_init(void); +int cpu_sh4_exec(CPUSH4State * s); +struct siginfo; +int cpu_sh4_signal_handler(int hostsignum, struct siginfo *info, + void *puc); + +#include "softfloat.h" + +#include "cpu-all.h" + +/* Memory access type */ +enum { + /* Privilege */ + ACCESS_PRIV = 0x01, + /* Direction */ + ACCESS_WRITE = 0x02, + /* Type of instruction */ + ACCESS_CODE = 0x10, + ACCESS_INT = 0x20 +}; + +/* MMU control register */ +#define MMUCR 0x1F000010 +#define MMUCR_AT (1<<0) +#define MMUCR_SV (1<<8) + +#endif /* _CPU_SH4_H */ diff --git a/target-sh4/exec.h b/target-sh4/exec.h new file mode 100644 index 0000000..c219fef --- /dev/null +++ b/target-sh4/exec.h @@ -0,0 +1,75 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef _EXEC_SH4_H +#define _EXEC_SH4_H + +#include "config.h" +#include "dyngen-exec.h" + +register struct CPUSH4State *env asm(AREG0); +register uint32_t T0 asm(AREG1); +register uint32_t T1 asm(AREG2); +register uint32_t T2 asm(AREG3); + +#include "cpu.h" +#include "exec-all.h" + +#ifndef CONFIG_USER_ONLY +#include "softmmu_exec.h" +#endif + +#define RETURN() __asm__ __volatile__("") + +static inline void regs_to_env(void) +{ + /* XXXXX */ +} + +static inline void env_to_regs(void) +{ + /* XXXXX */ +} + +int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, + int is_user, int is_softmmu); + +int find_itlb_entry(CPUState * env, target_ulong address, + int use_asid, int update); +int find_utlb_entry(CPUState * env, target_ulong address, int use_asid); + +void helper_addc_T0_T1(void); +void helper_addv_T0_T1(void); +void helper_div1_T0_T1(void); +void helper_dmulsl_T0_T1(void); +void helper_dmulul_T0_T1(void); +void helper_macl_T0_T1(void); +void helper_macw_T0_T1(void); +void helper_negc_T0(void); +void helper_subc_T0_T1(void); +void helper_subv_T0_T1(void); +void helper_rotcl(uint32_t * addr); +void helper_rotcr(uint32_t * addr); + +void do_interrupt(CPUState * env); + +void cpu_loop_exit(void); +void do_raise_exception(void); + +#endif /* _EXEC_SH4_H */ diff --git a/target-sh4/helper.c b/target-sh4/helper.c new file mode 100644 index 0000000..5ab505a --- /dev/null +++ b/target-sh4/helper.c @@ -0,0 +1,398 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> +#include <signal.h> +#include <assert.h> + +#include "cpu.h" +#include "exec-all.h" + +#define MMU_OK 0 +#define MMU_ITLB_MISS (-1) +#define MMU_ITLB_MULTIPLE (-2) +#define MMU_ITLB_VIOLATION (-3) +#define MMU_DTLB_MISS_READ (-4) +#define MMU_DTLB_MISS_WRITE (-5) +#define MMU_DTLB_INITIAL_WRITE (-6) +#define MMU_DTLB_VIOLATION_READ (-7) +#define MMU_DTLB_VIOLATION_WRITE (-8) +#define MMU_DTLB_MULTIPLE (-9) +#define MMU_DTLB_MISS (-10) + +void do_interrupt(CPUState * env) +{ + if (loglevel & CPU_LOG_INT) { + const char *expname; + switch (env->exception_index) { + case 0x0e0: + expname = "addr_error"; + break; + case 0x040: + expname = "tlb_miss"; + break; + case 0x0a0: + expname = "tlb_violation"; + break; + case 0x180: + expname = "illegal_instruction"; + break; + case 0x1a0: + expname = "slot_illegal_instruction"; + break; + case 0x800: + expname = "fpu_disable"; + break; + case 0x820: + expname = "slot_fpu"; + break; + case 0x100: + expname = "data_write"; + break; + case 0x060: + expname = "dtlb_miss_write"; + break; + case 0x0c0: + expname = "dtlb_violation_write"; + break; + case 0x120: + expname = "fpu_exception"; + break; + case 0x080: + expname = "initial_page_write"; + break; + case 0x160: + expname = "trapa"; + break; + default: + expname = "???"; + break; + } + fprintf(logfile, "exception 0x%03x [%s] raised\n", + env->exception_index, expname); + cpu_dump_state(env, logfile, fprintf, 0); + } + + env->ssr = env->sr; + env->spc = env->spc; + env->sgr = env->gregs[15]; + env->sr |= SR_BL | SR_MD | SR_RB; + + env->expevt = env->exception_index & 0x7ff; + switch (env->exception_index) { + case 0x040: + case 0x060: + case 0x080: + env->pc = env->vbr + 0x400; + break; + case 0x140: + env->pc = 0xa0000000; + break; + default: + env->pc = env->vbr + 0x100; + break; + } +} + +static void update_itlb_use(CPUState * env, int itlbnb) +{ + uint8_t or_mask = 0, and_mask = (uint8_t) - 1; + + switch (itlbnb) { + case 0: + and_mask = 0x7f; + break; + case 1: + and_mask = 0xe7; + or_mask = 0x80; + break; + case 2: + and_mask = 0xfb; + or_mask = 0x50; + break; + case 3: + or_mask = 0x2c; + break; + } + + env->mmucr &= (and_mask << 24); + env->mmucr |= (or_mask << 24); +} + +static int itlb_replacement(CPUState * env) +{ + if ((env->mmucr & 0xe0000000) == 0xe0000000) + return 0; + if ((env->mmucr & 0x98000000) == 0x08000000) + return 1; + if ((env->mmucr & 0x54000000) == 0x04000000) + return 2; + if ((env->mmucr & 0x2c000000) == 0x00000000) + return 3; + assert(0); +} + +/* Find the corresponding entry in the right TLB + Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE +*/ +static int find_tlb_entry(CPUState * env, target_ulong address, + tlb_t * entries, uint8_t nbtlb, int use_asid) +{ + int match = MMU_DTLB_MISS; + uint32_t start, end; + uint8_t asid; + int i; + + asid = env->pteh & 0xff; + + for (i = 0; i < nbtlb; i++) { + if (!entries[i].v) + continue; /* Invalid entry */ + if (use_asid && entries[i].asid != asid && !entries[i].sh) + continue; /* Bad ASID */ +#if 0 + switch (entries[i].sz) { + case 0: + size = 1024; /* 1kB */ + break; + case 1: + size = 4 * 1024; /* 4kB */ + break; + case 2: + size = 64 * 1024; /* 64kB */ + break; + case 3: + size = 1024 * 1024; /* 1MB */ + break; + default: + assert(0); + } +#endif + start = (entries[i].vpn << 10) & ~(entries[i].size - 1); + end = start + entries[i].size - 1; + if (address >= start && address <= end) { /* Match */ + if (match != -1) + return MMU_DTLB_MULTIPLE; /* Multiple match */ + match = i; + } + } + return match; +} + +/* Find itlb entry - update itlb from utlb if necessary and asked for + Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE + Update the itlb from utlb if update is not 0 +*/ +int find_itlb_entry(CPUState * env, target_ulong address, + int use_asid, int update) +{ + int e, n; + + e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); + if (e == MMU_DTLB_MULTIPLE) + e = MMU_ITLB_MULTIPLE; + else if (e == MMU_DTLB_MISS && update) { + e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); + if (e >= 0) { + n = itlb_replacement(env); + env->itlb[n] = env->utlb[e]; + e = n; + } + } + if (e >= 0) + update_itlb_use(env, e); + return e; +} + +/* Find utlb entry + Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */ +int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) +{ + uint8_t urb, urc; + + /* Increment URC */ + urb = ((env->mmucr) >> 18) & 0x3f; + urc = ((env->mmucr) >> 10) & 0x3f; + urc++; + if (urc == urb || urc == UTLB_SIZE - 1) + urc = 0; + env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); + + /* Return entry */ + return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); +} + +/* Match address against MMU + Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE, + MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ, + MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS, + MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION +*/ +static int get_mmu_address(CPUState * env, target_ulong * physical, + int *prot, target_ulong address, + int rw, int access_type) +{ + int use_asid, is_code, n; + tlb_t *matching = NULL; + + use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0; + is_code = env->pc == address; /* Hack */ + + /* Use a hack to find if this is an instruction or data access */ + if (env->pc == address && !(rw & PAGE_WRITE)) { + n = find_itlb_entry(env, address, use_asid, 1); + if (n >= 0) { + matching = &env->itlb[n]; + if ((env->sr & SR_MD) & !(matching->pr & 2)) + n = MMU_ITLB_VIOLATION; + else + *prot = PAGE_READ; + } + } else { + n = find_utlb_entry(env, address, use_asid); + if (n >= 0) { + matching = &env->utlb[n]; + switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) { + case 0: /* 000 */ + case 2: /* 010 */ + n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE : + MMU_DTLB_VIOLATION_READ; + break; + case 1: /* 001 */ + case 4: /* 100 */ + case 5: /* 101 */ + if (rw & PAGE_WRITE) + n = MMU_DTLB_VIOLATION_WRITE; + else + *prot = PAGE_READ; + break; + case 3: /* 011 */ + case 6: /* 110 */ + case 7: /* 111 */ + *prot = rw & (PAGE_READ | PAGE_WRITE); + break; + } + } else if (n == MMU_DTLB_MISS) { + n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : + MMU_DTLB_MISS_READ; + } + } + if (n >= 0) { + *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | + (address & (matching->size - 1)); + if ((rw & PAGE_WRITE) & !matching->d) + n = MMU_DTLB_INITIAL_WRITE; + else + n = MMU_OK; + } + return n; +} + +int get_physical_address(CPUState * env, target_ulong * physical, + int *prot, target_ulong address, + int rw, int access_type) +{ + /* P1, P2 and P4 areas do not use translation */ + if ((address >= 0x80000000 && address < 0xc0000000) || + address >= 0xe0000000) { + if (!(env->sr & SR_MD) + && (address < 0xe0000000 || address > 0xe4000000)) { + /* Unauthorized access in user mode (only store queues are available) */ + fprintf(stderr, "Unauthorized access\n"); + return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE : + MMU_DTLB_MISS_READ; + } + /* Mask upper 3 bits */ + *physical = address & 0x1FFFFFFF; + *prot = PAGE_READ | PAGE_WRITE; + return MMU_OK; + } + + /* If MMU is disabled, return the corresponding physical page */ + if (!env->mmucr & MMUCR_AT) { + *physical = address & 0x1FFFFFFF; + *prot = PAGE_READ | PAGE_WRITE; + return MMU_OK; + } + + /* We need to resort to the MMU */ + return get_mmu_address(env, physical, prot, address, rw, access_type); +} + +int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, + int is_user, int is_softmmu) +{ + target_ulong physical, page_offset, page_size; + int prot, ret, access_type; + + /* XXXXX */ +#if 0 + fprintf(stderr, "%s pc %08x ad %08x rw %d is_user %d smmu %d\n", + __func__, env->pc, address, rw, is_user, is_softmmu); +#endif + + access_type = ACCESS_INT; + ret = + get_physical_address(env, &physical, &prot, address, rw, + access_type); + + if (ret != MMU_OK) { + env->tea = address; + switch (ret) { + case MMU_ITLB_MISS: + case MMU_DTLB_MISS_READ: + env->exception_index = 0x040; + break; + case MMU_DTLB_MULTIPLE: + case MMU_ITLB_MULTIPLE: + env->exception_index = 0x140; + break; + case MMU_ITLB_VIOLATION: + env->exception_index = 0x0a0; + break; + case MMU_DTLB_MISS_WRITE: + env->exception_index = 0x060; + break; + case MMU_DTLB_INITIAL_WRITE: + env->exception_index = 0x080; + break; + case MMU_DTLB_VIOLATION_READ: + env->exception_index = 0x0a0; + break; + case MMU_DTLB_VIOLATION_WRITE: + env->exception_index = 0x0c0; + break; + default: + assert(0); + } + return 1; + } + + page_size = TARGET_PAGE_SIZE; + page_offset = + (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1); + address = (address & TARGET_PAGE_MASK) + page_offset; + physical = (physical & TARGET_PAGE_MASK) + page_offset; + + return tlb_set_page(env, address, physical, prot, is_user, is_softmmu); +} diff --git a/target-sh4/op.c b/target-sh4/op.c new file mode 100644 index 0000000..dbab658 --- /dev/null +++ b/target-sh4/op.c @@ -0,0 +1,882 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include "exec.h" + +static inline void set_flag(uint32_t flag) +{ + env->flags |= flag; +} + +static inline void clr_flag(uint32_t flag) +{ + env->flags &= ~flag; +} + +static inline void set_t(void) +{ + env->sr |= SR_T; +} + +static inline void clr_t(void) +{ + env->sr &= ~SR_T; +} + +static inline void cond_t(int cond) +{ + if (cond) + set_t(); + else + clr_t(); +} + +void OPPROTO op_movl_imm_T0(void) +{ + T0 = (uint32_t) PARAM1; + RETURN(); +} + +void OPPROTO op_movl_imm_T1(void) +{ + T0 = (uint32_t) PARAM1; + RETURN(); +} + +void OPPROTO op_movl_imm_T2(void) +{ + T0 = (uint32_t) PARAM1; + RETURN(); +} + +void OPPROTO op_cmp_eq_imm_T0(void) +{ + cond_t((int32_t) T0 == (int32_t) PARAM1); + RETURN(); +} + +void OPPROTO op_cmd_eq_T0_T1(void) +{ + cond_t(T0 == T1); + RETURN(); +} + +void OPPROTO op_cmd_hs_T0_T1(void) +{ + cond_t((uint32_t) T0 <= (uint32_t) T1); + RETURN(); +} + +void OPPROTO op_cmd_ge_T0_T1(void) +{ + cond_t((int32_t) T0 <= (int32_t) T1); + RETURN(); +} + +void OPPROTO op_cmd_hi_T0_T1(void) +{ + cond_t((uint32_t) T0 < (uint32_t) T1); + RETURN(); +} + +void OPPROTO op_cmd_gt_T0_T1(void) +{ + cond_t((int32_t) T0 < (int32_t) T1); + RETURN(); +} + +void OPPROTO op_not_T0(void) +{ + T0 = ~T0; + RETURN(); +} + +void OPPROTO op_bf_s(void) +{ + T2 = ~env->sr; + env->delayed_pc = PARAM1; + set_flag(DELAY_SLOT_CONDITIONAL); + RETURN(); +} + +void OPPROTO op_bt_s(void) +{ + T2 = env->sr; + env->delayed_pc = PARAM1; + set_flag(DELAY_SLOT_CONDITIONAL); + RETURN(); +} + +void OPPROTO op_bra(void) +{ + env->delayed_pc = PARAM1; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_braf_T0(void) +{ + env->delayed_pc = PARAM1 + T0; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_bsr(void) +{ + env->pr = PARAM1; + env->delayed_pc = PARAM2; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_bsrf_T0(void) +{ + env->pr = PARAM1; + env->delayed_pc = PARAM1 + T0; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_jsr_T0(void) +{ + env->pr = PARAM1; + env->delayed_pc = T0; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_rts(void) +{ + env->delayed_pc = env->pr; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_clr_delay_slot(void) +{ + clr_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_clr_delay_slot_conditional(void) +{ + clr_flag(DELAY_SLOT_CONDITIONAL); + RETURN(); +} + +void OPPROTO op_exit_tb(void) +{ + EXIT_TB(); + RETURN(); +} + +void OPPROTO op_addl_imm_T0(void) +{ + T0 += PARAM1; + RETURN(); +} + +void OPPROTO op_addl_imm_T1(void) +{ + T1 += PARAM1; + RETURN(); +} + +void OPPROTO op_clrmac(void) +{ + env->mach = env->macl = 0; + RETURN(); +} + +void OPPROTO op_clrs(void) +{ + env->sr &= ~SR_S; + RETURN(); +} + +void OPPROTO op_clrt(void) +{ + env->sr &= ~SR_T; + RETURN(); +} + +void OPPROTO op_sets(void) +{ + env->sr |= SR_S; + RETURN(); +} + +void OPPROTO op_sett(void) +{ + env->sr |= SR_T; + RETURN(); +} + +void OPPROTO op_rte(void) +{ + env->sr = env->ssr; + env->delayed_pc = env->spc; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_swapb_T0(void) +{ + T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); + RETURN(); +} + +void OPPROTO op_swapw_T0(void) +{ + T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); + RETURN(); +} + +void OPPROTO op_xtrct_T0_T1(void) +{ + T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); + RETURN(); +} + +void OPPROTO op_addc_T0_T1(void) +{ + helper_addc_T0_T1(); + RETURN(); +} + +void OPPROTO op_addv_T0_T1(void) +{ + helper_addv_T0_T1(); + RETURN(); +} + +void OPPROTO op_cmp_eq_T0_T1(void) +{ + cond_t(T1 == T0); + RETURN(); +} + +void OPPROTO op_cmp_ge_T0_T1(void) +{ + cond_t((int32_t) T1 >= (int32_t) T0); + RETURN(); +} + +void OPPROTO op_cmp_gt_T0_T1(void) +{ + cond_t((int32_t) T1 > (int32_t) T0); + RETURN(); +} + +void OPPROTO op_cmp_hi_T0_T1(void) +{ + cond_t((uint32_t) T1 > (uint32_t) T0); + RETURN(); +} + +void OPPROTO op_cmp_hs_T0_T1(void) +{ + cond_t((uint32_t) T1 >= (uint32_t) T0); + RETURN(); +} + +void OPPROTO op_cmp_str_T0_T1(void) +{ + cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || + (T0 & 0x0000ff00) == (T1 & 0x0000ff00) || + (T0 & 0x00ff0000) == (T1 & 0x00ff0000) || + (T0 & 0xff000000) == (T1 & 0xff000000)); + RETURN(); +} + +void OPPROTO op_tst_T0_T1(void) +{ + cond_t((T1 & T0) == 0); + RETURN(); +} + +void OPPROTO op_div0s_T0_T1(void) +{ + if (T1 & 0x80000000) + env->sr |= SR_Q; + else + env->sr &= ~SR_Q; + if (T0 & 0x80000000) + env->sr |= SR_M; + else + env->sr &= ~SR_M; + cond_t((T1 ^ T0) & 0x80000000); + RETURN(); +} + +void OPPROTO op_div0u(void) +{ + env->sr &= ~(SR_M | SR_Q | SR_T); + RETURN(); +} + +void OPPROTO op_div1_T0_T1(void) +{ + helper_div1_T0_T1(); + RETURN(); +} + +void OPPROTO op_dmulsl_T0_T1(void) +{ + helper_dmulsl_T0_T1(); + RETURN(); +} + +void OPPROTO op_dmulul_T0_T1(void) +{ + helper_dmulul_T0_T1(); + RETURN(); +} + +void OPPROTO op_macl_T0_T1(void) +{ + helper_macl_T0_T1(); + RETURN(); +} + +void OPPROTO op_macw_T0_T1(void) +{ + helper_macw_T0_T1(); + RETURN(); +} + +void OPPROTO op_mull_T0_T1(void) +{ + env->macl = (T0 * T1) & 0xffffffff; + RETURN(); +} + +void OPPROTO op_mulsw_T0_T1(void) +{ + env->macl = (int32_t) T0 *(int32_t) T1; + RETURN(); +} + +void OPPROTO op_muluw_T0_T1(void) +{ + env->macl = (uint32_t) T0 *(uint32_t) T1; + RETURN(); +} + +void OPPROTO op_neg_T0(void) +{ + T0 = -T0; + RETURN(); +} + +void OPPROTO op_negc_T0(void) +{ + helper_negc_T0(); + RETURN(); +} + +void OPPROTO op_shad_T0_T1(void) +{ + if ((T0 & 0x80000000) == 0) + T1 <<= (T0 & 0x1f); + else if ((T0 & 0x1f) == 0) + T1 = 0; + else + T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); + RETURN(); +} + +void OPPROTO op_shld_T0_T1(void) +{ + if ((T0 & 0x80000000) == 0) + T1 <<= (T0 & 0x1f); + else if ((T0 & 0x1f) == 0) + T1 = 0; + else + T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); + RETURN(); +} + +void OPPROTO op_subc_T0_T1(void) +{ + helper_subc_T0_T1(); + RETURN(); +} + +void OPPROTO op_subv_T0_T1(void) +{ + helper_subv_T0_T1(); + RETURN(); +} + +void OPPROTO op_trapa(void) +{ + env->tra = PARAM1 * 2; + env->exception_index = 0x160; + do_raise_exception(); + RETURN(); +} + +void OPPROTO op_cmp_pl_T0(void) +{ + cond_t((int32_t) T0 > 0); + RETURN(); +} + +void OPPROTO op_cmp_pz_T0(void) +{ + cond_t((int32_t) T0 >= 0); + RETURN(); +} + +void OPPROTO op_jmp_T0(void) +{ + env->delayed_pc = T0; + set_flag(DELAY_SLOT); + RETURN(); +} + +void OPPROTO op_movl_rN_rN(void) +{ + env->gregs[PARAM2] = env->gregs[PARAM1]; + RETURN(); +} + +void OPPROTO op_ldcl_rMplus_rN_bank(void) +{ + env->gregs[PARAM2] = env->gregs[PARAM1]; + env->gregs[PARAM1] += 4; + RETURN(); +} + +#define LDSTOPS(target,load,store) \ +void OPPROTO op_##load##_T0_##target (void) \ +{ env ->target = T0; RETURN(); \ +} \ +void OPPROTO op_##store##_##target##_T0 (void) \ +{ T0 = env->target; RETURN(); \ +} \ + +LDSTOPS(sr, ldc, stc) + LDSTOPS(gbr, ldc, stc) + LDSTOPS(vbr, ldc, stc) + LDSTOPS(ssr, ldc, stc) + LDSTOPS(spc, ldc, stc) + LDSTOPS(sgr, ldc, stc) + LDSTOPS(dbr, ldc, stc) + LDSTOPS(mach, lds, sts) + LDSTOPS(macl, lds, sts) + LDSTOPS(pr, lds, sts) + +void OPPROTO op_movt_rN(void) +{ + env->gregs[PARAM1] = env->sr & SR_T; + RETURN(); +} + +void OPPROTO op_rotcl_Rn(void) +{ + helper_rotcl(&env->gregs[PARAM1]); + RETURN(); +} + +void OPPROTO op_rotcr_Rn(void) +{ + helper_rotcr(&env->gregs[PARAM1]); + RETURN(); +} + +void OPPROTO op_rotl_Rn(void) +{ + cond_t(env->gregs[PARAM1] & 0x80000000); + env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T); + RETURN(); +} + +void OPPROTO op_rotr_Rn(void) +{ + cond_t(env->gregs[PARAM1] & 1); + env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) | + ((env->sr & SR_T) ? 0x80000000 : 0); + RETURN(); +} + +void OPPROTO op_shal_Rn(void) +{ + cond_t(env->gregs[PARAM1] & 0x80000000); + env->gregs[PARAM1] <<= 1; + RETURN(); +} + +void OPPROTO op_shar_Rn(void) +{ + cond_t(env->gregs[PARAM1] & 1); + *(int32_t *) & env->gregs[PARAM1] >>= 1; + RETURN(); +} + +void OPPROTO op_shlr_Rn(void) +{ + cond_t(env->gregs[PARAM1] & 1); + *(uint32_t *) & env->gregs[PARAM1] >>= 1; + RETURN(); +} + +void OPPROTO op_shll2_Rn(void) +{ + env->gregs[PARAM1] <<= 2; + RETURN(); +} + +void OPPROTO op_shll8_Rn(void) +{ + env->gregs[PARAM1] <<= 8; + RETURN(); +} + +void OPPROTO op_shll16_Rn(void) +{ + env->gregs[PARAM1] <<= 16; + RETURN(); +} + +void OPPROTO op_shlr2_Rn(void) +{ + *(uint32_t *) & env->gregs[PARAM1] >>= 2; + RETURN(); +} + +void OPPROTO op_shlr8_Rn(void) +{ + *(uint32_t *) & env->gregs[PARAM1] >>= 8; + RETURN(); +} + +void OPPROTO op_shlr16_Rn(void) +{ + *(uint32_t *) & env->gregs[PARAM1] >>= 16; + RETURN(); +} + +void OPPROTO op_tasb_rN(void) +{ + cond_t(*(int8_t *) env->gregs[PARAM1] == 0); + *(int8_t *) env->gregs[PARAM1] |= 0x80; + RETURN(); +} + +void OPPROTO op_movl_T0_rN(void) +{ + env->gregs[PARAM1] = T0; + RETURN(); +} + +void OPPROTO op_movl_T1_rN(void) +{ + env->gregs[PARAM1] = T1; + RETURN(); +} + +void OPPROTO op_movb_rN_T0(void) +{ + T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff); + RETURN(); +} + +void OPPROTO op_movub_rN_T0(void) +{ + T0 = env->gregs[PARAM1] & 0xff; + RETURN(); +} + +void OPPROTO op_movw_rN_T0(void) +{ + T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff); + RETURN(); +} + +void OPPROTO op_movuw_rN_T0(void) +{ + T0 = env->gregs[PARAM1] & 0xffff; + RETURN(); +} + +void OPPROTO op_movl_rN_T0(void) +{ + T0 = env->gregs[PARAM1]; + RETURN(); +} + +void OPPROTO op_movb_rN_T1(void) +{ + T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff); + RETURN(); +} + +void OPPROTO op_movub_rN_T1(void) +{ + T1 = env->gregs[PARAM1] & 0xff; + RETURN(); +} + +void OPPROTO op_movw_rN_T1(void) +{ + T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff); + RETURN(); +} + +void OPPROTO op_movuw_rN_T1(void) +{ + T1 = env->gregs[PARAM1] & 0xffff; + RETURN(); +} + +void OPPROTO op_movl_rN_T1(void) +{ + T1 = env->gregs[PARAM1]; + RETURN(); +} + +void OPPROTO op_movl_imm_rN(void) +{ + env->gregs[PARAM2] = PARAM1; + RETURN(); +} + +void OPPROTO op_dec1_rN(void) +{ + env->gregs[PARAM1] -= 1; + RETURN(); +} + +void OPPROTO op_dec2_rN(void) +{ + env->gregs[PARAM1] -= 2; + RETURN(); +} + +void OPPROTO op_dec4_rN(void) +{ + env->gregs[PARAM1] -= 4; + RETURN(); +} + +void OPPROTO op_inc1_rN(void) +{ + env->gregs[PARAM1] += 1; + RETURN(); +} + +void OPPROTO op_inc2_rN(void) +{ + env->gregs[PARAM1] += 2; + RETURN(); +} + +void OPPROTO op_inc4_rN(void) +{ + env->gregs[PARAM1] += 4; + RETURN(); +} + +void OPPROTO op_add_T0_rN(void) +{ + env->gregs[PARAM1] += T0; + RETURN(); +} + +void OPPROTO op_sub_T0_rN(void) +{ + env->gregs[PARAM1] -= T0; + RETURN(); +} + +void OPPROTO op_and_T0_rN(void) +{ + env->gregs[PARAM1] &= T0; + RETURN(); +} + +void OPPROTO op_or_T0_rN(void) +{ + env->gregs[PARAM1] |= T0; + RETURN(); +} + +void OPPROTO op_xor_T0_rN(void) +{ + env->gregs[PARAM1] ^= T0; + RETURN(); +} + +void OPPROTO op_add_rN_T0(void) +{ + T0 += env->gregs[PARAM1]; + RETURN(); +} + +void OPPROTO op_add_rN_T1(void) +{ + T1 += env->gregs[PARAM1]; + RETURN(); +} + +void OPPROTO op_add_imm_rN(void) +{ + env->gregs[PARAM2] += PARAM1; + RETURN(); +} + +void OPPROTO op_and_imm_rN(void) +{ + env->gregs[PARAM2] &= PARAM1; + RETURN(); +} + +void OPPROTO op_or_imm_rN(void) +{ + env->gregs[PARAM2] |= PARAM1; + RETURN(); +} + +void OPPROTO op_xor_imm_rN(void) +{ + env->gregs[PARAM2] ^= PARAM1; + RETURN(); +} + +void OPPROTO op_dt_rN(void) +{ + cond_t((--env->gregs[PARAM1]) == 0); + RETURN(); +} + +void OPPROTO op_tst_imm_rN(void) +{ + cond_t((env->gregs[PARAM2] & PARAM1) == 0); + RETURN(); +} + +void OPPROTO op_movl_T0_T1(void) +{ + T1 = T0; + RETURN(); +} + +void OPPROTO op_goto_tb0(void) +{ + GOTO_TB(op_goto_tb0, PARAM1, 0); + RETURN(); +} + +void OPPROTO op_goto_tb1(void) +{ + GOTO_TB(op_goto_tb1, PARAM1, 1); + RETURN(); +} + +void OPPROTO op_movl_imm_PC(void) +{ + env->pc = PARAM1; + RETURN(); +} + +void OPPROTO op_jT(void) +{ + if (env->sr & SR_T) + GOTO_LABEL_PARAM(1); + RETURN(); +} + +void OPPROTO op_jTT2(void) +{ + if (T2 & SR_T) + GOTO_LABEL_PARAM(1); + RETURN(); +} + +void OPPROTO op_movl_delayed_pc_PC(void) +{ + env->pc = env->delayed_pc; + RETURN(); +} + +void OPPROTO op_addl_GBR_T0(void) +{ + T0 += env->gbr; + RETURN(); +} + +void OPPROTO op_and_imm_T0(void) +{ + T0 &= PARAM1; + RETURN(); +} + +void OPPROTO op_or_imm_T0(void) +{ + T0 |= PARAM1; + RETURN(); +} + +void OPPROTO op_xor_imm_T0(void) +{ + T0 ^= PARAM1; + RETURN(); +} + +void OPPROTO op_tst_imm_T0(void) +{ + cond_t((T0 & PARAM1) == 0); + RETURN(); +} + +void OPPROTO op_raise_illegal_instruction(void) +{ + env->exception_index = 0x180; + do_raise_exception(); + RETURN(); +} + +void OPPROTO op_raise_slot_illegal_instruction(void) +{ + env->exception_index = 0x1a0; + do_raise_exception(); + RETURN(); +} + +void OPPROTO op_debug(void) +{ + env->exception_index = EXCP_DEBUG; + cpu_loop_exit(); +} + +/* Load and store */ +#define MEMSUFFIX _raw +#include "op_mem.c" +#undef MEMSUFFIX +#if !defined(CONFIG_USER_ONLY) +#define MEMSUFFIX _user +#include "op_mem.c" +#undef MEMSUFFIX + +#define MEMSUFFIX _kernel +#include "op_mem.c" +#undef MEMSUFFIX +#endif diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c new file mode 100644 index 0000000..1c63fe5 --- /dev/null +++ b/target-sh4/op_helper.c @@ -0,0 +1,372 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <assert.h> +#include "exec.h" + +void cpu_loop_exit(void) +{ + longjmp(env->jmp_env, 1); +} + +void do_raise_exception(void) +{ + cpu_loop_exit(); +} + +#ifndef CONFIG_USER_ONLY + +#define MMUSUFFIX _mmu +#define GETPC() (__builtin_return_address(0)) + +#define SHIFT 0 +#include "softmmu_template.h" + +#define SHIFT 1 +#include "softmmu_template.h" + +#define SHIFT 2 +#include "softmmu_template.h" + +#define SHIFT 3 +#include "softmmu_template.h" + +void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) +{ + TranslationBlock *tb; + CPUState *saved_env; + unsigned long pc; + int ret; + + /* XXX: hack to restore env in all cases, even if not called from + generated code */ + saved_env = env; + env = cpu_single_env; + ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, is_user, 1); + if (ret) { + if (retaddr) { + /* now we have a real cpu fault */ + pc = (unsigned long) retaddr; + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, NULL); + } + } + do_raise_exception(); + } + env = saved_env; +} + +#endif + +void helper_addc_T0_T1(void) +{ + uint32_t tmp0, tmp1; + + tmp1 = T0 + T1; + tmp0 = T1; + T1 = tmp1 + (env->sr & 1); + if (tmp0 > tmp1) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + if (tmp1 > T1) + env->sr |= SR_T; +} + +void helper_addv_T0_T1(void) +{ + uint32_t dest, src, ans; + + if ((int32_t) T1 >= 0) + dest = 0; + else + dest = 1; + if ((int32_t) T0 >= 0) + src = 0; + else + src = 1; + src += dest; + T1 += T0; + if ((int32_t) T1 >= 0) + ans = 0; + else + ans = 1; + ans += dest; + if (src == 0 || src == 2) { + if (ans == 1) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + } else + env->sr &= ~SR_T; +} + +#define T (env->sr & SR_T) +#define Q (env->sr & SR_Q ? 1 : 0) +#define M (env->sr & SR_M ? 1 : 0) +#define SETT env->sr |= SR_T +#define CLRT env->sr &= ~SR_T +#define SETQ env->sr |= SR_Q +#define CLRQ env->sr &= ~SR_Q +#define SETM env->sr |= SR_M +#define CLRM env->sr &= ~SR_M + +void helper_div1_T0_T1(void) +{ + uint32_t tmp0, tmp2; + uint8_t old_q, tmp1 = 0xff; + + printf("div1 T0=0x%08x T1=0x%08x M=%d Q=%d T=%d\n", T0, T1, M, Q, T); + old_q = Q; + if ((0x80000000 & T1) != 0) + SETQ; + else + CLRQ; + tmp2 = T0; + T1 <<= 1; + T1 |= T; + switch (old_q) { + case 0: + switch (M) { + case 0: + tmp0 = T1; + T1 -= tmp2; + tmp1 = T1 > tmp0; + switch (Q) { + case 0: + if (tmp1) + SETQ; + else + CLRQ; + break; + case 1: + if (tmp1 == 0) + SETQ; + else + CLRQ; + break; + } + break; + case 1: + tmp0 = T1; + T1 += tmp2; + tmp1 = T1 < tmp0; + switch (Q) { + case 0: + if (tmp1 == 0) + SETQ; + else + CLRQ; + break; + case 1: + if (tmp1) + SETQ; + else + CLRQ; + break; + } + break; + } + break; + case 1: + switch (M) { + case 0: + tmp0 = T1; + T1 += tmp2; + tmp1 = T1 < tmp0; + switch (Q) { + case 0: + if (tmp1) + SETQ; + else + CLRQ; + break; + case 1: + if (tmp1 == 0) + SETQ; + else + CLRQ; + break; + } + break; + case 1: + tmp0 = T1; + T1 -= tmp2; + tmp1 = T1 > tmp0; + switch (Q) { + case 0: + if (tmp1 == 0) + SETQ; + else + CLRQ; + break; + case 1: + if (tmp1) + SETQ; + else + CLRQ; + break; + } + break; + } + break; + } + if (Q == M) + SETT; + else + CLRT; + printf("Output: T1=0x%08x M=%d Q=%d T=%d\n", T1, M, Q, T); +} + +void helper_dmulsl_T0_T1() +{ + int64_t res; + + res = (int64_t) (int32_t) T0 *(int64_t) (int32_t) T1; + env->mach = (res >> 32) & 0xffffffff; + env->macl = res & 0xffffffff; +} + +void helper_dmulul_T0_T1() +{ + uint64_t res; + + res = (uint64_t) (uint32_t) T0 *(uint64_t) (uint32_t) T1; + env->mach = (res >> 32) & 0xffffffff; + env->macl = res & 0xffffffff; +} + +void helper_macl_T0_T1() +{ + int64_t res; + + res = ((uint64_t) env->mach << 32) | env->macl; + res += (int64_t) (int32_t) T0 *(int64_t) (int32_t) T1; + env->mach = (res >> 32) & 0xffffffff; + env->macl = res & 0xffffffff; + if (env->sr & SR_S) { + if (res < 0) + env->mach |= 0xffff0000; + else + env->mach &= 0x00007fff; + } +} + +void helper_macw_T0_T1() +{ + int64_t res; + + res = ((uint64_t) env->mach << 32) | env->macl; + res += (int64_t) (int16_t) T0 *(int64_t) (int16_t) T1; + env->mach = (res >> 32) & 0xffffffff; + env->macl = res & 0xffffffff; + if (env->sr & SR_S) { + if (res < -0x80000000) { + env->mach = 1; + env->macl = 0x80000000; + } else if (res > 0x000000007fffffff) { + env->mach = 1; + env->macl = 0x7fffffff; + } + } +} + +void helper_negc_T0() +{ + uint32_t temp; + + temp = -T0; + T0 = temp - (env->sr & SR_T); + if (0 < temp) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + if (temp < T0) + env->sr |= SR_T; +} + +void helper_subc_T0_T1() +{ + uint32_t tmp0, tmp1; + + tmp1 = T1 - T0; + tmp0 = T1; + T1 = tmp1 - (env->sr & SR_T); + if (tmp0 < tmp1) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + if (tmp1 < T1) + env->sr |= SR_T; +} + +void helper_subv_T0_T1() +{ + int32_t dest, src, ans; + + if ((int32_t) T1 >= 0) + dest = 0; + else + dest = 1; + if ((int32_t) T0 >= 0) + src = 0; + else + src = 1; + src += dest; + T1 -= T0; + if ((int32_t) T1 >= 0) + ans = 0; + else + ans = 1; + ans += dest; + if (src == 1) { + if (ans == 1) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + } else + env->sr &= ~SR_T; +} + +void helper_rotcl(uint32_t * addr) +{ + uint32_t new; + + new = (*addr << 1) | (env->sr & SR_T); + if (*addr & 0x80000000) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + *addr = new; +} + +void helper_rotcr(uint32_t * addr) +{ + uint32_t new; + + new = (*addr >> 1) | ((env->sr & SR_T) ? 0x80000000 : 0); + if (*addr & 1) + env->sr |= SR_T; + else + env->sr &= ~SR_T; + *addr = new; +} diff --git a/target-sh4/op_mem.c b/target-sh4/op_mem.c new file mode 100644 index 0000000..9ab75f4 --- /dev/null +++ b/target-sh4/op_mem.c @@ -0,0 +1,58 @@ +/* + * SH4 emulation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +void glue(op_ldb_T0_T0, MEMSUFFIX) (void) { + T0 = glue(ldsb, MEMSUFFIX) (T0); + RETURN(); +} + +void glue(op_ldub_T0_T0, MEMSUFFIX) (void) { + T0 = glue(ldub, MEMSUFFIX) (T0); + RETURN(); +} + +void glue(op_stb_T0_T1, MEMSUFFIX) (void) { + glue(stb, MEMSUFFIX) (T1, T0); + RETURN(); +} + +void glue(op_ldw_T0_T0, MEMSUFFIX) (void) { + T0 = glue(ldsw, MEMSUFFIX) (T0); + RETURN(); +} + +void glue(op_lduw_T0_T0, MEMSUFFIX) (void) { + T0 = glue(lduw, MEMSUFFIX) (T0); + RETURN(); +} + +void glue(op_stw_T0_T1, MEMSUFFIX) (void) { + glue(stw, MEMSUFFIX) (T1, T0); + RETURN(); +} + +void glue(op_ldl_T0_T0, MEMSUFFIX) (void) { + T0 = glue(ldl, MEMSUFFIX) (T0); + RETURN(); +} + +void glue(op_stl_T0_T1, MEMSUFFIX) (void) { + glue(stl, MEMSUFFIX) (T1, T0); + RETURN(); +} diff --git a/target-sh4/translate.c b/target-sh4/translate.c new file mode 100644 index 0000000..0013e49 --- /dev/null +++ b/target-sh4/translate.c @@ -0,0 +1,1073 @@ +/* + * SH4 translation + * + * Copyright (c) 2005 Samuel Tardieu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include <stdarg.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <inttypes.h> +#include <assert.h> + +#define DEBUG_DISAS +#define SH4_DEBUG_DISAS +//#define SH4_SINGLE_STEP + +#include "cpu.h" +#include "exec-all.h" +#include "disas.h" + +enum { +#define DEF(s, n, copy_size) INDEX_op_ ## s, +#include "opc.h" +#undef DEF + NB_OPS, +}; + +#ifdef USE_DIRECT_JUMP +#define TBPARAM(x) +#else +#define TBPARAM(x) ((long)(x)) +#endif + +static uint16_t *gen_opc_ptr; +static uint32_t *gen_opparam_ptr; + +#include "gen-op.h" + +typedef struct DisasContext { + struct TranslationBlock *tb; + target_ulong pc; + uint32_t sr; + uint16_t opcode; + uint32_t flags; + int memidx; + uint32_t delayed_pc; + int singlestep_enabled; +} DisasContext; + +#ifdef CONFIG_USER_ONLY + +#define GEN_OP_LD(width) \ + void gen_op_ld##width##_T0_T0 (DisasContext *ctx) { \ + gen_op_ld##width##_T0_T0_raw(); \ + } +#define GEN_OP_ST(width) \ + void gen_op_st##width##_T0_T1 (DisasContext *ctx) { \ + gen_op_st##width##_T0_T1_raw(); \ + } + +#else + +#define GEN_OP_LD(width) \ + void gen_op_ld##width##_T0_T0 (DisasContext *ctx) { \ + if (ctx->memidx) gen_op_ld##width##_T0_T0_kernel(); \ + else gen_op_ld##width##_T0_T0_user();\ + } +#define GEN_OP_ST(width) \ + void gen_op_st##width##_T0_T1 (DisasContext *ctx) { \ + if (ctx->memidx) gen_op_st##width##_T0_T1_kernel(); \ + else gen_op_st##width##_T0_T1_user();\ + } + +#endif + +GEN_OP_LD(ub) + GEN_OP_LD(b) + GEN_OP_ST(b) + GEN_OP_LD(uw) + GEN_OP_LD(w) + GEN_OP_ST(w) + GEN_OP_LD(l) + GEN_OP_ST(l) + +void cpu_dump_state(CPUState * env, FILE * f, + int (*cpu_fprintf) (FILE * f, const char *fmt, ...), + int flags) +{ + int i; + cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x\n", + env->pc, env->sr, env->pr); + for (i = 0; i < 24; i += 4) { + cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", + i, env->gregs[i], i + 1, env->gregs[i + 1], + i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); + } + if (env->flags & DELAY_SLOT) { + cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", + env->delayed_pc); + } else if (env->flags & DELAY_SLOT_CONDITIONAL) { + cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", + env->delayed_pc); + } +} + +void cpu_sh4_reset(CPUSH4State * env) +{ + env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ + env->vbr = 0; + env->pc = 0xA0000000; + env->fpscr = 0x00040001; + env->mmucr = 0; +} + +CPUSH4State *cpu_sh4_init(void) +{ + CPUSH4State *env; + + env = qemu_mallocz(sizeof(CPUSH4State)); + if (!env) + return NULL; + cpu_exec_init(env); + cpu_sh4_reset(env); + tlb_flush(env, 1); + return env; +} + +#ifdef CONFIG_USER_ONLY +target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +{ + return addr; +} +#else +target_ulong cpu_get_phys_page_debug(CPUState * env, target_ulong addr) +{ + target_ulong physical; + int prot; + + get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0); + return physical; +} +#endif + +static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) +{ + TranslationBlock *tb; + tb = ctx->tb; + + if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && + !ctx->singlestep_enabled) { + /* Use a direct jump if in same page and singlestep not enabled */ + if (n == 0) + gen_op_goto_tb0(TBPARAM(tb)); + else + gen_op_goto_tb1(TBPARAM(tb)); + gen_op_movl_imm_T0((long) tb + n); + } else { + gen_op_movl_imm_T0(0); + } + gen_op_movl_imm_PC(dest); + if (ctx->singlestep_enabled) + gen_op_debug(); + gen_op_exit_tb(); +} + +/* Jump to pc after an exception */ +static void gen_jump_exception(DisasContext * ctx) +{ + gen_op_movl_imm_T0(0); + if (ctx->singlestep_enabled) + gen_op_debug(); + gen_op_exit_tb(); +} + +static void gen_jump(DisasContext * ctx) +{ + if (ctx->delayed_pc == (uint32_t) - 1) { + /* Target is not statically known, it comes necessarily from a + delayed jump as immediate jump are conditinal jumps */ + gen_op_movl_delayed_pc_PC(); + gen_op_movl_imm_T0(0); + if (ctx->singlestep_enabled) + gen_op_debug(); + gen_op_exit_tb(); + } else { + gen_goto_tb(ctx, 0, ctx->delayed_pc); + } +} + +/* Immediate conditional jump (bt or bf) */ +static void gen_conditional_jump(DisasContext * ctx, + target_ulong ift, target_ulong ifnott) +{ + int l1; + + l1 = gen_new_label(); + gen_op_jT(l1); + gen_goto_tb(ctx, 0, ifnott); + gen_set_label(l1); + gen_goto_tb(ctx, 1, ift); +} + +/* Delayed conditional jump (bt or bf) */ +static void gen_delayed_conditional_jump(DisasContext * ctx) +{ + int l1; + + l1 = gen_new_label(); + gen_op_jTT2(l1); + gen_goto_tb(ctx, 0, ctx->pc); + gen_set_label(l1); + gen_goto_tb(ctx, 1, ctx->delayed_pc); +} + +#define B3_0 (ctx->opcode & 0xf) +#define B6_4 ((ctx->opcode >> 4) & 0x7) +#define B7_4 ((ctx->opcode >> 4) & 0xf) +#define B7_0 (ctx->opcode & 0xff) +#define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) +#define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ + (ctx->opcode & 0xfff)) +#define B11_8 ((ctx->opcode >> 8) & 0xf) +#define B15_12 ((ctx->opcode >> 12) & 0xf) + +#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ + (x) + 16 : (x)) + +#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ + ? (x) + 16 : (x)) + +#define CHECK_NOT_DELAY_SLOT \ + if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \ + {gen_op_raise_slot_illegal_instruction (); ctx->flags |= BRANCH_EXCEPTION; \ + return;} + +void decode_opc(DisasContext * ctx) +{ +#if 0 + fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); +#endif + switch (ctx->opcode) { + case 0x0019: /* div0u */ + printf("div0u\n"); + gen_op_div0u(); + return; + case 0x000b: /* rts */ + CHECK_NOT_DELAY_SLOT gen_op_rts(); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; + case 0x0028: /* clrmac */ + gen_op_clrmac(); + return; + case 0x0048: /* clrs */ + gen_op_clrs(); + return; + case 0x0008: /* clrt */ + gen_op_clrt(); + return; + case 0x0038: /* ldtlb */ + assert(0); /* XXXXX */ + return; + case 0x004b: /* rte */ + CHECK_NOT_DELAY_SLOT gen_op_rte(); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; + case 0x0058: /* sets */ + gen_op_sets(); + return; + case 0x0018: /* sett */ + gen_op_sett(); + return; + case 0xfbfb: /* frchg */ + assert(0); /* XXXXX */ + return; + case 0xf3fb: /* fschg */ + assert(0); /* XXXXX */ + return; + case 0x0009: /* nop */ + return; + case 0x001b: /* sleep */ + assert(0); /* XXXXX */ + return; + } + + switch (ctx->opcode & 0xf000) { + case 0x1000: /* mov.l Rm,@(disp,Rn) */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_addl_imm_T1(B3_0 * 4); + gen_op_stl_T0_T1(ctx); + return; + case 0x5000: /* mov.l @(disp,Rm),Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_addl_imm_T0(B3_0 * 4); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0xe000: /* mov.l #imm,Rn */ + gen_op_movl_imm_rN(B7_0s, REG(B11_8)); + return; + case 0x9000: /* mov.w @(disp,PC),Rn */ + gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0xd000: /* mov.l @(disp,PC),Rn */ + gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x7000: /* add.l #imm,Rn */ + gen_op_add_imm_rN(B7_0s, REG(B11_8)); + return; + case 0xa000: /* bra disp */ + CHECK_NOT_DELAY_SLOT + gen_op_bra(ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2); + ctx->flags |= DELAY_SLOT; + return; + case 0xb000: /* bsr disp */ + CHECK_NOT_DELAY_SLOT + gen_op_bsr(ctx->pc + 4, ctx->delayed_pc = + ctx->pc + 4 + B11_0s * 2); + ctx->flags |= DELAY_SLOT; + return; + } + + switch (ctx->opcode & 0xf00f) { + case 0x6003: /* mov Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x2000: /* mov.b Rm,@Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stb_T0_T1(ctx); + return; + case 0x2001: /* mov.w Rm,@Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stw_T0_T1(ctx); + return; + case 0x2002: /* mov.l Rm,@Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stl_T0_T1(ctx); + return; + case 0x6000: /* mov.b @Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldb_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x6001: /* mov.w @Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x6002: /* mov.l @Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x2004: /* mov.b Rm,@-Rn */ + gen_op_dec1_rN(REG(B11_8)); + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stb_T0_T1(ctx); + return; + case 0x2005: /* mov.w Rm,@-Rn */ + gen_op_dec2_rN(REG(B11_8)); + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stw_T0_T1(ctx); + return; + case 0x2006: /* mov.l Rm,@-Rn */ + gen_op_dec4_rN(REG(B11_8)); + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stl_T0_T1(ctx); + return; + case 0x6004: /* mov.l @Rm+,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldb_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + gen_op_inc1_rN(REG(B7_4)); + return; + case 0x6005: /* mov.w @Rm+,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + gen_op_inc2_rN(REG(B7_4)); + return; + case 0x6006: /* mov.l @Rm+,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + gen_op_inc4_rN(REG(B7_4)); + return; + case 0x0004: /* mov.b Rm,@(R0,Rn) */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_add_rN_T1(REG(0)); + gen_op_stb_T0_T1(ctx); + return; + case 0x0005: /* mov.w Rm,@(R0,Rn) */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_add_rN_T1(REG(0)); + gen_op_stw_T0_T1(ctx); + return; + case 0x0006: /* mov.l Rm,@(R0,Rn) */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_add_rN_T1(REG(0)); + gen_op_stl_T0_T1(ctx); + return; + case 0x000c: /* mov.b @(R0,Rm),Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_add_rN_T0(REG(0)); + gen_op_ldb_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x000d: /* mov.w @(R0,Rm),Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_add_rN_T0(REG(0)); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x000e: /* mov.l @(R0,Rm),Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_add_rN_T0(REG(0)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x6008: /* swap.b Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_swapb_T0(); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x6009: /* swap.w Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_swapw_T0(); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x200d: /* xtrct Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_xtrct_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x300c: /* add Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_add_T0_rN(REG(B11_8)); + return; + case 0x300e: /* addc Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_addc_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x300f: /* addv Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_addv_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x2009: /* and Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_and_T0_rN(REG(B11_8)); + return; + case 0x3000: /* cmp/eq Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_eq_T0_T1(); + return; + case 0x3003: /* cmp/ge Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_ge_T0_T1(); + return; + case 0x3007: /* cmp/gt Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_gt_T0_T1(); + return; + case 0x3006: /* cmp/hi Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_hi_T0_T1(); + return; + case 0x3002: /* cmp/hs Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_hs_T0_T1(); + return; + case 0x200c: /* cmp/str Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_cmp_str_T0_T1(); + return; + case 0x2007: /* div0s Rm,Rn */ + printf("div0s\n"); + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_div0s_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x3004: /* div1 Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_div1_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x300d: /* dmuls.l Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_dmulsl_T0_T1(); + return; + case 0x3005: /* dmulu.l Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_dmulul_T0_T1(); + return; + case 0x600e: /* exts.b Rm,Rn */ + gen_op_movb_rN_T0(REG(B7_4)); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x600f: /* exts.w Rm,Rn */ + gen_op_movw_rN_T0(REG(B7_4)); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x600c: /* extu.b Rm,Rn */ + gen_op_movub_rN_T0(REG(B7_4)); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x600d: /* extu.w Rm,Rn */ + gen_op_movuw_rN_T0(REG(B7_4)); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x000f: /* mac.l @Rm+,@Rn- */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_T1(); + gen_op_movl_rN_T1(REG(B7_4)); + gen_op_ldl_T0_T0(ctx); + gen_op_macl_T0_T1(); + gen_op_inc4_rN(REG(B7_4)); + gen_op_inc4_rN(REG(B11_8)); + return; + case 0x400f: /* mac.w @Rm+,@Rn+ */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_T1(); + gen_op_movl_rN_T1(REG(B7_4)); + gen_op_ldl_T0_T0(ctx); + gen_op_macw_T0_T1(); + gen_op_inc2_rN(REG(B7_4)); + gen_op_inc2_rN(REG(B11_8)); + return; + case 0x0007: /* mul.l Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_mull_T0_T1(); + return; + case 0x200f: /* muls.w Rm,Rn */ + gen_op_movw_rN_T0(REG(B7_4)); + gen_op_movw_rN_T1(REG(B11_8)); + gen_op_mulsw_T0_T1(); + return; + case 0x200e: /* mulu.w Rm,Rn */ + gen_op_movuw_rN_T0(REG(B7_4)); + gen_op_movuw_rN_T1(REG(B11_8)); + gen_op_muluw_T0_T1(); + return; + case 0x600b: /* neg Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_neg_T0(); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x600a: /* negc Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_negc_T0(); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x6007: /* not Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_not_T0(); + gen_op_movl_T0_rN(REG(B11_8)); + return; + case 0x200b: /* or Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_or_T0_rN(REG(B11_8)); + return; + case 0x400c: /* shad Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_shad_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x400d: /* shld Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_shld_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x3008: /* sub Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_sub_T0_rN(REG(B11_8)); + return; + case 0x300a: /* subc Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_subc_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x300b: /* subv Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_subv_T0_T1(); + gen_op_movl_T1_rN(REG(B11_8)); + return; + case 0x2008: /* tst Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_tst_T0_T1(); + return; + case 0x200a: /* xor Rm,Rn */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_xor_T0_rN(REG(B11_8)); + return; + } + + switch (ctx->opcode & 0xff00) { + case 0xc900: /* and #imm,R0 */ + gen_op_and_imm_rN(B7_0, REG(0)); + return; + case 0xcd00: /* and.b #imm,@(R0+GBR) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_addl_GBR_T0(); + gen_op_movl_T0_T1(); + gen_op_ldb_T0_T0(ctx); + gen_op_and_imm_T0(B7_0); + gen_op_stb_T0_T1(ctx); + return; + case 0x8b00: /* bf label */ + CHECK_NOT_DELAY_SLOT + gen_conditional_jump(ctx, ctx->pc + 2, + ctx->pc + 4 + B7_0s * 2); + ctx->flags |= BRANCH_CONDITIONAL; + return; + case 0x8f00: /* bf/s label */ + CHECK_NOT_DELAY_SLOT + gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); + ctx->flags |= DELAY_SLOT_CONDITIONAL; + return; + case 0x8900: /* bt label */ + CHECK_NOT_DELAY_SLOT + gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, + ctx->pc + 2); + ctx->flags |= BRANCH_CONDITIONAL; + return; + case 0x8d00: /* bt/s label */ + CHECK_NOT_DELAY_SLOT + gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2); + ctx->flags |= DELAY_SLOT_CONDITIONAL; + return; + case 0x8800: /* cmp/eq #imm,R0 */ + gen_op_movl_rN_T0(REG(0)); + gen_op_cmp_eq_imm_T0(B7_0s); + return; + case 0xc400: /* mov.b @(disp,GBR),R0 */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_ldb_T0_T0(ctx); + gen_op_movl_T0_rN(REG(0)); + return; + case 0xc500: /* mov.w @(disp,GBR),R0 */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(0)); + return; + case 0xc600: /* mov.l @(disp,GBR),R0 */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(REG(0)); + return; + case 0xc000: /* mov.b R0,@(disp,GBR) */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_movl_T0_T1(); + gen_op_movl_rN_T0(REG(0)); + gen_op_stb_T0_T1(ctx); + return; + case 0xc100: /* mov.w R0,@(disp,GBR) */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_movl_T0_T1(); + gen_op_movl_rN_T0(REG(0)); + gen_op_stw_T0_T1(ctx); + return; + case 0xc200: /* mov.l R0,@(disp,GBR) */ + gen_op_stc_gbr_T0(); + gen_op_addl_imm_T0(B7_0); + gen_op_movl_T0_T1(); + gen_op_movl_rN_T0(REG(0)); + gen_op_stl_T0_T1(ctx); + return; + case 0x8000: /* mov.b R0,@(disp,Rn) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_movl_rN_T1(REG(B7_4)); + gen_op_addl_imm_T1(B3_0); + gen_op_stb_T0_T1(ctx); + return; + case 0x8100: /* mov.w R0,@(disp,Rn) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_movl_rN_T1(REG(B7_4)); + gen_op_addl_imm_T1(B3_0 * 2); + gen_op_stw_T0_T1(ctx); + return; + case 0x8400: /* mov.b @(disp,Rn),R0 */ + gen_op_movl_rN_T0(REG(0)); + gen_op_movl_rN_T1(REG(B7_4)); + gen_op_addl_imm_T1(B3_0); + gen_op_stb_T0_T1(ctx); + return; + case 0x8500: /* mov.w @(disp,Rn),R0 */ + gen_op_movl_rN_T0(REG(B7_4)); + gen_op_addl_imm_T0(B3_0 * 2); + gen_op_ldw_T0_T0(ctx); + gen_op_movl_T0_rN(REG(0)); + return; + case 0xc700: /* mova @(disp,PC),R0 */ + gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3, + REG(0)); + return; + case 0xcb00: /* or #imm,R0 */ + gen_op_or_imm_rN(B7_0, REG(0)); + return; + case 0xcf00: /* or.b #imm,@(R0+GBR) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_addl_GBR_T0(); + gen_op_movl_T0_T1(); + gen_op_ldb_T0_T0(ctx); + gen_op_or_imm_T0(B7_0); + gen_op_stb_T0_T1(ctx); + return; + case 0xc300: /* trapa #imm */ + CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc); + gen_op_trapa(B7_0); + ctx->flags |= BRANCH; + return; + case 0xc800: /* tst #imm,R0 */ + gen_op_tst_imm_rN(B7_0, REG(0)); + return; + case 0xcc00: /* tst #imm,@(R0+GBR) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_addl_GBR_T0(); + gen_op_ldb_T0_T0(ctx); + gen_op_tst_imm_T0(B7_0); + return; + case 0xca00: /* xor #imm,R0 */ + gen_op_xor_imm_rN(B7_0, REG(0)); + return; + case 0xce00: /* xor.b #imm,@(R0+GBR) */ + gen_op_movl_rN_T0(REG(0)); + gen_op_addl_GBR_T0(); + gen_op_movl_T0_T1(); + gen_op_ldb_T0_T0(ctx); + gen_op_xor_imm_T0(B7_0); + gen_op_stb_T0_T1(ctx); + return; + } + + switch (ctx->opcode & 0xf08f) { + case 0x408e: /* ldc Rm,Rn_BANK */ + gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4)); + return; + case 0x4087: /* ldc.l @Rm+,Rn_BANK */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + gen_op_movl_T0_rN(ALTREG(B6_4)); + gen_op_inc4_rN(REG(B11_8)); + return; + case 0x0082: /* stc Rm_BANK,Rn */ + gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8)); + return; + case 0x4083: /* stc.l Rm_BANK,@-Rn */ + gen_op_dec4_rN(REG(B11_8)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_movl_rN_T0(ALTREG(B6_4)); + gen_op_stl_T0_T1(ctx); + return; + } + + switch (ctx->opcode & 0xf0ff) { + case 0x0023: /* braf Rn */ + CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); + gen_op_braf_T0(ctx->pc + 4); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; + case 0x0003: /* bsrf Rn */ + CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); + gen_op_bsrf_T0(ctx->pc + 4); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; + case 0x4015: /* cmp/pl Rn */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_cmp_pl_T0(); + return; + case 0x4011: /* cmp/pz Rn */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_cmp_pz_T0(); + return; + case 0x4010: /* dt Rn */ + gen_op_dt_rN(REG(B11_8)); + return; + case 0x402b: /* jmp @Rn */ + CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); + gen_op_jmp_T0(); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; + case 0x400b: /* jsr @Rn */ + CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8)); + gen_op_jsr_T0(ctx->pc + 4); + ctx->flags |= DELAY_SLOT; + ctx->delayed_pc = (uint32_t) - 1; + return; +#define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald) \ + case ldnum: \ + gen_op_movl_rN_T0 (REG(B11_8)); \ + gen_op_##ldop##_T0_##reg (); \ + extrald \ + return; \ + case ldpnum: \ + gen_op_movl_rN_T0 (REG(B11_8)); \ + gen_op_ldl_T0_T0 (ctx); \ + gen_op_inc4_rN (REG(B11_8)); \ + gen_op_##ldop##_T0_##reg (); \ + extrald \ + return; \ + case stnum: \ + gen_op_##stop##_##reg##_T0 (); \ + gen_op_movl_T0_rN (REG(B11_8)); \ + return; \ + case stpnum: \ + gen_op_##stop##_##reg##_T0 (); \ + gen_op_dec4_rN (REG(B11_8)); \ + gen_op_movl_rN_T1 (REG(B11_8)); \ + gen_op_stl_T0_T1 (ctx); \ + return; + LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->flags |= + MODE_CHANGE; + ) + LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,) + LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,) + LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,) + LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,) + LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,) + LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,) + LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,) + LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,) + case 0x00c3: /* movca.l R0,@Rm */ + gen_op_movl_rN_T0(REG(0)); + gen_op_movl_rN_T1(REG(B11_8)); + gen_op_stl_T0_T1(ctx); + return; + case 0x0029: /* movt Rn */ + gen_op_movt_rN(REG(B11_8)); + return; + case 0x0093: /* ocbi @Rn */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + return; + case 0x00a2: /* ocbp @Rn */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + return; + case 0x00b3: /* ocbwb @Rn */ + gen_op_movl_rN_T0(REG(B11_8)); + gen_op_ldl_T0_T0(ctx); + return; + case 0x0083: /* pref @Rn */ + return; + case 0x4024: /* rotcl Rn */ + gen_op_rotcl_Rn(REG(B11_8)); + return; + case 0x4025: /* rotcr Rn */ + gen_op_rotcr_Rn(REG(B11_8)); + return; + case 0x4004: /* rotl Rn */ + gen_op_rotl_Rn(REG(B11_8)); + return; + case 0x4005: /* rotr Rn */ + gen_op_rotr_Rn(REG(B11_8)); + return; + case 0x4000: /* shll Rn */ + case 0x4020: /* shal Rn */ + gen_op_shal_Rn(REG(B11_8)); + return; + case 0x4021: /* shar Rn */ + gen_op_shar_Rn(REG(B11_8)); + return; + case 0x4001: /* shlr Rn */ + gen_op_shlr_Rn(REG(B11_8)); + return; + case 0x4008: /* shll2 Rn */ + gen_op_shll2_Rn(REG(B11_8)); + return; + case 0x4018: /* shll8 Rn */ + gen_op_shll8_Rn(REG(B11_8)); + return; + case 0x4028: /* shll16 Rn */ + gen_op_shll16_Rn(REG(B11_8)); + return; + case 0x4009: /* shlr2 Rn */ + gen_op_shlr2_Rn(REG(B11_8)); + return; + case 0x4019: /* shlr8 Rn */ + gen_op_shlr8_Rn(REG(B11_8)); + return; + case 0x4029: /* shlr16 Rn */ + gen_op_shlr16_Rn(REG(B11_8)); + return; + case 0x401b: /* tas.b @Rn */ + gen_op_tasb_rN(REG(B11_8)); + return; + } + + fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", + ctx->opcode, ctx->pc); + gen_op_raise_illegal_instruction(); + ctx->flags |= BRANCH_EXCEPTION; +} + +int gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, + int search_pc) +{ + DisasContext ctx; + target_ulong pc_start; + static uint16_t *gen_opc_end; + uint32_t old_flags; + int i; + + pc_start = tb->pc; + gen_opc_ptr = gen_opc_buf; + gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; + gen_opparam_ptr = gen_opparam_buf; + ctx.pc = pc_start; + ctx.flags = env->flags; + old_flags = 0; + ctx.sr = env->sr; + ctx.memidx = (env->sr & SR_MD) ? 1 : 0; + ctx.delayed_pc = env->delayed_pc; + ctx.tb = tb; + ctx.singlestep_enabled = env->singlestep_enabled; + nb_gen_labels = 0; + +#ifdef DEBUG_DISAS + if (loglevel & CPU_LOG_TB_CPU) { + fprintf(logfile, + "------------------------------------------------\n"); + cpu_dump_state(env, logfile, fprintf, 0); + } +#endif + + while ((old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) == 0 && + (ctx.flags & (BRANCH | BRANCH_CONDITIONAL | MODE_CHANGE | + BRANCH_EXCEPTION)) == 0 && + gen_opc_ptr < gen_opc_end && ctx.sr == env->sr) { + old_flags = ctx.flags; + if (env->nb_breakpoints > 0) { + for (i = 0; i < env->nb_breakpoints; i++) { + if (ctx.pc == env->breakpoints[i]) { + /* We have hit a breakpoint - make sure PC is up-to-date */ + gen_op_movl_imm_PC(ctx.pc); + gen_op_debug(); + ctx.flags |= BRANCH_EXCEPTION; + break; + } + } + } +#if 0 + fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); + fflush(stderr); +#endif + ctx.opcode = lduw_code(ctx.pc); + decode_opc(&ctx); + ctx.pc += 2; + if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) + break; + if (env->singlestep_enabled) + break; +#ifdef SH4_SINGLE_STEP + break; +#endif + } + + switch (old_flags & (DELAY_SLOT_CONDITIONAL | DELAY_SLOT)) { + case DELAY_SLOT_CONDITIONAL: + gen_op_clr_delay_slot_conditional(); + gen_delayed_conditional_jump(&ctx); + break; + case DELAY_SLOT: + gen_op_clr_delay_slot(); + gen_jump(&ctx); + break; + case 0: + if (ctx.flags & BRANCH_EXCEPTION) { + gen_jump_exception(&ctx); + } else if ((ctx.flags & (BRANCH | BRANCH_CONDITIONAL)) == 0) { + gen_goto_tb(&ctx, 0, ctx.pc); + } + break; + default: + /* Both cannot be set at the same time */ + assert(0); + } + + if (env->singlestep_enabled) { + gen_op_debug(); + } + *gen_opc_ptr = INDEX_op_end; + tb->size = ctx.pc - pc_start; + +#ifdef DEBUG_DISAS +#ifdef SH4_DEBUG_DISAS + if (loglevel & CPU_LOG_TB_IN_ASM) + fprintf(logfile, "\n"); +#endif + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ + target_disas(logfile, pc_start, ctx.pc - pc_start, 0); + fprintf(logfile, "\n"); + } + if (loglevel & CPU_LOG_TB_OP) { + fprintf(logfile, "OP:\n"); + dump_ops(gen_opc_buf, gen_opparam_buf); + fprintf(logfile, "\n"); + } +#endif + return 0; +} + +int gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) +{ + return gen_intermediate_code_internal(env, tb, 0); +} + +int gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) +{ + assert(0); + return gen_intermediate_code_internal(env, tb, 1); +} |