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authorPeter Maydell <peter.maydell@linaro.org>2015-08-25 13:34:57 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-08-25 13:34:57 +0100
commit34a4450434f1a5daee06fca223afcbb9c8f1ee24 (patch)
tree8512b8209e81b928f79352d48f66fcc35a7a63da /target-sh4/translate.c
parenta30878e708c2149ce07d709a8b62edd944628449 (diff)
parentb76f21a70748b735d6ac84fec4bb9bdaafa339b1 (diff)
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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into staging
queued tcg patches # gpg: Signature made Mon 24 Aug 2015 19:37:15 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20150824: linux-user: remove useless macros GUEST_BASE and RESERVED_VA linux-user: remove --enable-guest-base/--disable-guest-base tcg/aarch64: Use softmmu fast path for unaligned accesses tcg/s390: Use softmmu fast path for unaligned accesses tcg/ppc: Improve unaligned load/store handling on 64-bit backend tcg/i386: use softmmu fast path for unaligned accesses tcg: Remove tcg_gen_trunc_i64_i32 tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32 tcg: update README about size changing ops tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops tcg: implement real ext_i32_i64 and extu_i32_i64 ops tcg: don't abuse TCG type in tcg_gen_trunc_shr_i64_i32 tcg: rename trunc_shr_i32 into trunc_shr_i64_i32 tcg/optimize: allow constant to have copies tcg/optimize: track const/copy status separately tcg/optimize: add temp_is_const and temp_is_copy functions tcg/optimize: optimize temps tracking tcg/optimize: fix constant signedness Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-sh4/translate.c')
-rw-r--r--target-sh4/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 3b4a1b5..be0cb32 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -288,10 +288,10 @@ static inline void gen_load_fpr64(TCGv_i64 t, int reg)
static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
{
TCGv_i32 tmp = tcg_temp_new_i32();
- tcg_gen_trunc_i64_i32(tmp, t);
+ tcg_gen_extrl_i64_i32(tmp, t);
tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
tcg_gen_shri_i64(t, t, 32);
- tcg_gen_trunc_i64_i32(tmp, t);
+ tcg_gen_extrl_i64_i32(tmp, t);
tcg_gen_mov_i32(cpu_fregs[reg], tmp);
tcg_temp_free_i32(tmp);
}