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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-02 19:39:11 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-09 21:07:03 +0100 |
| commit | e0bcb9ca36e4f3081c7e6841283646985ed9676b (patch) | |
| tree | 966a3463050e3ea20ff252e85412b3e176bceb80 /target-sh4/helper.c | |
| parent | 434254aa5f1a9497710dd10993a72ec434e149a6 (diff) | |
| download | qemu-e0bcb9ca36e4f3081c7e6841283646985ed9676b.zip qemu-e0bcb9ca36e4f3081c7e6841283646985ed9676b.tar.gz qemu-e0bcb9ca36e4f3081c7e6841283646985ed9676b.tar.bz2 | |
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-sh4/helper.c')
| -rw-r--r-- | target-sh4/helper.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 088d36a..e7c494f 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env) entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); } + void cpu_sh4_invalidate_tlb(CPUSH4State *s) +{ + int i; + + /* UTLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + /* ITLB */ + for (i = 0; i < UTLB_SIZE; i++) { + tlb_t * entry = &s->utlb[i]; + entry->v = 0; + } + + tlb_flush(s, 1); +} + void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, uint32_t mem_value) { |