SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).

Main purpose of this is to delete
       *physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.

Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.

Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 0 insertions, 12 deletions

diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index f077462..c2cc432 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -439,19 +439,7 @@ int get_physical_address(CPUState * env, target_ulong * physical,
 	if (address >= 0x80000000 && address < 0xc0000000) {
 	    /* Mask upper 3 bits for P1 and P2 areas */
 	    *physical = address & 0x1fffffff;
-        } else if (address >= 0xfd000000 && address < 0xfe000000) {
-            /* PCI memory space */
-            *physical = address;
-	} else if (address >= 0xfc000000) {
-	    /*
-	     * Mask upper 3 bits for control registers in P4 area,
-	     * to unify access to control registers via P0-P3 area.
-	     * The addresses for cache store queue, TLB address array
-	     * are not masked.
-	     */
-	*physical = address & 0x1fffffff;
 	} else {
-	    /* access to cache store queue, or TLB address array. */
 	    *physical = address;
 	}
 	*prot = PAGE_READ | PAGE_WRITE;