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| author | Aurelien Jarno <aurelien@aurel32.net> | 2015-05-25 01:47:30 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2015-06-05 01:37:58 +0200 |
| commit | 92892330e78ffca7bebf03f4f7161c5bbd6602d2 (patch) | |
| tree | 166e993da0bb3d33cc9c626286cbea1c46c66a21 /target-s390x | |
| parent | 4a33565f9f46145d8cc701ab623b18bf423c469e (diff) | |
| download | qemu-92892330e78ffca7bebf03f4f7161c5bbd6602d2.zip qemu-92892330e78ffca7bebf03f4f7161c5bbd6602d2.tar.gz qemu-92892330e78ffca7bebf03f4f7161c5bbd6602d2.tar.bz2 | |
target-s390x: move a few instructions to the correct facility
LY is part of the long-displacement facility.
RISBHG and RISBLG are part of the high-word facility.
STCMH is part of the z/Architecture.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-s390x')
| -rw-r--r-- | target-s390x/insn-data.def | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 72c3a2e..e10aa6b 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -336,7 +336,7 @@ /* LOAD */ C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0) C(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0) - C(0xe358, LY, RXY_a, Z, 0, a2, new, r1_32, ld32s, 0) + C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0) C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0) C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0) C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0) @@ -595,8 +595,8 @@ /* ROTATE THEN INSERT SELECTED BITS */ C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64) - C(0xec5d, RISBHG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) - C(0xec51, RISBLG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) + C(0xec5d, RISBHG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) + C(0xec51, RISBLG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) /* ROTATE_THEN <OP> SELECTED BITS */ C(0xec54, RNSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) C(0xec56, ROSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) @@ -670,7 +670,7 @@ /* STORE CHARACTERS UNDER MASK */ D(0xbe00, STCM, RS_b, Z, r1_o, a2, 0, 0, stcm, 0, 0) D(0xeb2d, STCMY, RSY_b, LD, r1_o, a2, 0, 0, stcm, 0, 0) - D(0xeb2c, STCMH, RSY_b, LD, r1_o, a2, 0, 0, stcm, 0, 32) + D(0xeb2c, STCMH, RSY_b, Z, r1_o, a2, 0, 0, stcm, 0, 32) /* STORE HALFWORD */ C(0x4000, STH, RX_a, Z, r1_o, a2, 0, 0, st16, 0) C(0xe370, STHY, RXY_a, LD, r1_o, a2, 0, 0, st16, 0) |