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authorj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-26 00:55:17 +0000
committerj_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>2007-10-26 00:55:17 +0000
commitf0685f6e7a4179e75c4696de88de9657c6a86e95 (patch)
treee33c78da9eea30e69c57b06f0f27a8c2fe0b9871 /target-ppc
parentdac454af57c6389c2e3df0b8b51a9b35429d8caa (diff)
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For consistency, align the address to the cache line before using it,
when invalidating the instruction cache. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3449 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/op_helper_mem.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/op_helper_mem.h b/target-ppc/op_helper_mem.h
index a395e02..e8aa640 100644
--- a/target-ppc/op_helper_mem.h
+++ b/target-ppc/op_helper_mem.h
@@ -252,8 +252,8 @@ void glue(do_icbi, MEMSUFFIX) (void)
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
- tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
T0 &= ~(env->icache_line_size - 1);
+ tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
tb_invalidate_page_range((uint32_t)T0,
(uint32_t)(T0 + env->icache_line_size));
}
@@ -267,8 +267,8 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
* (not a fetch) by the MMU. To be sure it will be so,
* do the load "by hand".
*/
- tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
T0 &= ~(env->icache_line_size - 1);
+ tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
tb_invalidate_page_range((uint64_t)T0,
(uint64_t)(T0 + env->icache_line_size));
}