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| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-08-28 19:15:07 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-11-04 23:26:10 +0100 |
| commit | e57d02022c4ba748fa6c0916319f9108c4502cb9 (patch) | |
| tree | 3bcf7536536bf2e929e8e118b24cd7f313ea9da2 /target-ppc | |
| parent | ebbd8b40a9f8dcc9ff048c2ce82a6219e4e80d38 (diff) | |
| download | qemu-e57d02022c4ba748fa6c0916319f9108c4502cb9.zip qemu-e57d02022c4ba748fa6c0916319f9108c4502cb9.tar.gz qemu-e57d02022c4ba748fa6c0916319f9108c4502cb9.tar.bz2 | |
ppc: rename gen_set_cr6_from_fpscr
It sets CR1, not CR6 (and the spec agrees).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/translate.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d03daea..d1deba7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8221,7 +8221,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) } #if defined(TARGET_PPC64) -static void gen_set_cr6_from_fpscr(DisasContext *ctx) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); @@ -8229,7 +8229,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx) tcg_temp_free_i32(tmp); } #else -static void gen_set_cr6_from_fpscr(DisasContext *ctx) +static void gen_set_cr1_from_fpscr(DisasContext *ctx) { tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); } @@ -8249,7 +8249,7 @@ static void gen_##name(DisasContext *ctx) \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, ra, rb); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rd); \ tcg_temp_free_ptr(ra); \ @@ -8307,7 +8307,7 @@ static void gen_##name(DisasContext *ctx) \ u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx) \ i32 = tcg_const_i32(i32fld(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, ra, rb, i32); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8352,7 +8352,7 @@ static void gen_##name(DisasContext *ctx) \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rb); \ @@ -8373,7 +8373,7 @@ static void gen_##name(DisasContext *ctx) \ i32 = tcg_const_i32(i32fld(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rs, i32); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ - gen_set_cr6_from_fpscr(ctx); \ + gen_set_cr1_from_fpscr(ctx); \ } \ tcg_temp_free_ptr(rt); \ tcg_temp_free_ptr(rs); \ |