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| author | Alexander Graf <agraf@suse.de> | 2012-06-20 21:19:09 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-06-24 01:04:51 +0200 |
| commit | 84755ed51e6266b115322834933ce404a2fbf3f9 (patch) | |
| tree | adf197626625cd0add9b4f2afb76aba17fe9b641 /target-ppc | |
| parent | 5025d5421d3c6e705669f365192a7edf17b1aad8 (diff) | |
| download | qemu-84755ed51e6266b115322834933ce404a2fbf3f9.zip qemu-84755ed51e6266b115322834933ce404a2fbf3f9.tar.gz qemu-84755ed51e6266b115322834933ce404a2fbf3f9.tar.bz2 | |
PPC: Add some booke SPR defines
The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 67e699c..12200ab 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1395,6 +1395,7 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_BOOKE_TLB1PS (0x159) #define SPR_BOOKE_TLB2PS (0x15A) #define SPR_BOOKE_TLB3PS (0x15B) +#define SPR_BOOKE_MAS7_MAS3 (0x174) #define SPR_BOOKE_IVOR0 (0x190) #define SPR_BOOKE_IVOR1 (0x191) #define SPR_BOOKE_IVOR2 (0x192) @@ -1762,6 +1763,27 @@ static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp) #define SPR_604_HID15 (0x3FF) #define SPR_E500_SVR (0x3FF) +/* Disable MAS Interrupt Updates for Hypervisor */ +#define EPCR_DMIUH (1 << 22) +/* Disable Guest TLB Management Instructions */ +#define EPCR_DGTMI (1 << 23) +/* Guest Interrupt Computation Mode */ +#define EPCR_GICM (1 << 24) +/* Interrupt Computation Mode */ +#define EPCR_ICM (1 << 25) +/* Disable Embedded Hypervisor Debug */ +#define EPCR_DUVD (1 << 26) +/* Instruction Storage Interrupt Directed to Guest State */ +#define EPCR_ISIGS (1 << 27) +/* Data Storage Interrupt Directed to Guest State */ +#define EPCR_DSIGS (1 << 28) +/* Instruction TLB Error Interrupt Directed to Guest State */ +#define EPCR_ITLBGS (1 << 29) +/* Data TLB Error Interrupt Directed to Guest State */ +#define EPCR_DTLBGS (1 << 30) +/* External Input Interrupt Directed to Guest State */ +#define EPCR_EXTGS (1 << 31) + /*****************************************************************************/ /* PowerPC Instructions types definitions */ enum { |