target-ppc: convert exceptions generation to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162

7 files changed, 75 insertions, 65 deletions

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index d3df2f2..88499b1 100644
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -94,8 +94,8 @@ static always_inline target_ulong rotl64 (target_ulong i, int n)
 #include "softmmu_exec.h"
 #endif /* !defined(CONFIG_USER_ONLY) */
 
-void do_raise_exception_err (uint32_t exception, int error_code);
-void do_raise_exception (uint32_t exception);
+void raise_exception_err (CPUState *env, int exception, int error_code);
+void raise_exception (CPUState *env, int exception);
 
 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
                           int rw, int access_type);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 2df7f64..15ff5cc 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -40,6 +40,24 @@
 //#define FLUSH_ALL_TLBS
 
 /*****************************************************************************/
+/* Exceptions processing */
+
+void raise_exception_err (CPUState *env, int exception, int error_code)
+{
+#if 0
+    printf("Raise exception %3x code : %d\n", exception, error_code);
+#endif
+    env->exception_index = exception;
+    env->error_code = error_code;
+    cpu_loop_exit();
+}
+
+void raise_exception (CPUState *env, int exception)
+{
+    helper_raise_exception_err(exception, 0);
+}
+
+/*****************************************************************************/
 /* PowerPC MMU emulation */
 
 #if defined(CONFIG_USER_ONLY)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9620e0d..6178a56 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -1,5 +1,8 @@
 #include "def-helper.h"
 
+DEF_HELPER_2(raise_exception_err, void, i32, i32)
+DEF_HELPER_0(raise_debug, void)
+
 DEF_HELPER_2(fcmpo, i32, i64, i64)
 DEF_HELPER_2(fcmpu, i32, i64, i64)
 
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 1ef5dbd..8b3dbca 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -26,17 +26,6 @@
 #include "helper_regs.h"
 #include "op_helper.h"
 
-/* Generate exceptions */
-void OPPROTO op_raise_exception_err (void)
-{
-    do_raise_exception_err(PARAM1, PARAM2);
-}
-
-void OPPROTO op_debug (void)
-{
-    do_raise_exception(EXCP_DEBUG);
-}
-
 #if !defined(CONFIG_USER_ONLY)
 /* Segment registers load and store */
 void OPPROTO op_load_sr (void)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index daaceec..4f7521b 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -46,21 +46,17 @@
 /*****************************************************************************/
 /* Exceptions processing helpers */
 
-void do_raise_exception_err (uint32_t exception, int error_code)
+void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
 {
-#if 0
-    printf("Raise exception %3x code : %d\n", exception, error_code);
-#endif
-    env->exception_index = exception;
-    env->error_code = error_code;
-    cpu_loop_exit();
+    raise_exception_err(env, exception, error_code);
 }
 
-void do_raise_exception (uint32_t exception)
+void helper_raise_debug (void)
 {
-    do_raise_exception_err(exception, 0);
+    raise_exception(env, EXCP_DEBUG);
 }
 
+
 /*****************************************************************************/
 /* Registers load and stores */
 target_ulong helper_load_cr (void)
@@ -430,7 +426,7 @@ static always_inline uint64_t fload_invalid_op_excp (int op)
         /* Update the floating-point enabled exception summary */
         env->fpscr |= 1 << FPSCR_FEX;
         if (msr_fe0 != 0 || msr_fe1 != 0)
-            do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
+            raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
     }
     return ret;
 }
@@ -445,8 +441,8 @@ static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t ar
         /* Update the floating-point enabled exception summary */
         env->fpscr |= 1 << FPSCR_FEX;
         if (msr_fe0 != 0 || msr_fe1 != 0) {
-            do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                                   POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
+            raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                                POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
         }
     } else {
         /* Set the result to infinity */
@@ -686,7 +682,7 @@ void helper_float_check_status (void)
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
         if (msr_fe0 != 0 || msr_fe1 != 0)
-            do_raise_exception_err(env->exception_index, env->error_code);
+            raise_exception_err(env, env->exception_index, env->error_code);
     } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
         float_overflow_excp();
     } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
@@ -699,7 +695,7 @@ void helper_float_check_status (void)
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
         if (msr_fe0 != 0 || msr_fe1 != 0)
-            do_raise_exception_err(env->exception_index, env->error_code);
+            raise_exception_err(env, env->exception_index, env->error_code);
     }
     RETURN();
 #endif
@@ -1356,7 +1352,7 @@ void do_store_msr (void)
     T0 = hreg_store_msr(env, T0, 0);
     if (T0 != 0) {
         env->interrupt_request |= CPU_INTERRUPT_EXITTB;
-        do_raise_exception(T0);
+        raise_exception(env, T0);
     }
 }
 
@@ -1417,7 +1413,7 @@ void do_tw (int flags)
                   ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
                   ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
                   ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
     }
 }
 
@@ -1429,7 +1425,7 @@ void do_td (int flags)
                   ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
                   ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
                   ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
 }
 #endif
 
@@ -1670,14 +1666,14 @@ void do_load_dcr (void)
         if (loglevel != 0) {
             fprintf(logfile, "No DCR environment\n");
         }
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                               POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                            POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
     } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
         if (loglevel != 0) {
             fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
         }
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                               POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                            POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
     } else {
         T0 = val;
     }
@@ -1689,14 +1685,14 @@ void do_store_dcr (void)
         if (loglevel != 0) {
             fprintf(logfile, "No DCR environment\n");
         }
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                               POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                            POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
     } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
         if (loglevel != 0) {
             fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
         }
-        do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                               POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+        raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                            POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
     }
 }
 
@@ -2454,7 +2450,7 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
                 cpu_restore_state(tb, env, pc, NULL);
             }
         }
-        do_raise_exception_err(env->exception_index, env->error_code);
+        raise_exception_err(env, env->exception_index, env->error_code);
     }
     env = saved_env;
 }
diff --git a/target-ppc/op_mem.h b/target-ppc/op_mem.h
index b504555..912ff65 100644
--- a/target-ppc/op_mem.h
+++ b/target-ppc/op_mem.h
@@ -103,9 +103,9 @@ void OPPROTO glue(op_lswx, MEMSUFFIX) (void)
     if (likely(T1 != 0)) {
         if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
                      (PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
-            do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                                   POWERPC_EXCP_INVAL |
-                                   POWERPC_EXCP_INVAL_LSWX);
+            raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                                POWERPC_EXCP_INVAL |
+                                POWERPC_EXCP_INVAL_LSWX);
         } else {
             glue(do_lsw, MEMSUFFIX)(PARAM1);
         }
@@ -120,9 +120,9 @@ void OPPROTO glue(op_lswx_64, MEMSUFFIX) (void)
     if (likely(T1 != 0)) {
         if (unlikely((PARAM1 < PARAM2 && (PARAM1 + T1) > PARAM2) ||
                      (PARAM1 < PARAM3 && (PARAM1 + T1) > PARAM3))) {
-            do_raise_exception_err(POWERPC_EXCP_PROGRAM,
-                                   POWERPC_EXCP_INVAL |
-                                   POWERPC_EXCP_INVAL_LSWX);
+            raise_exception_err(env, POWERPC_EXCP_PROGRAM,
+                                POWERPC_EXCP_INVAL |
+                                POWERPC_EXCP_INVAL_LSWX);
         } else {
             glue(do_lsw_64, MEMSUFFIX)(PARAM1);
         }
@@ -282,7 +282,7 @@ PPC_LDF_OP_64(fs_le, ldfsr);
 void OPPROTO glue(op_lwarx, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu32, MEMSUFFIX)((uint32_t)T0);
         env->reserve = (uint32_t)T0;
@@ -294,7 +294,7 @@ void OPPROTO glue(op_lwarx, MEMSUFFIX) (void)
 void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu32, MEMSUFFIX)((uint64_t)T0);
         env->reserve = (uint64_t)T0;
@@ -305,7 +305,7 @@ void OPPROTO glue(op_lwarx_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_ldarx, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu64, MEMSUFFIX)((uint32_t)T0);
         env->reserve = (uint32_t)T0;
@@ -316,7 +316,7 @@ void OPPROTO glue(op_ldarx, MEMSUFFIX) (void)
 void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu64, MEMSUFFIX)((uint64_t)T0);
         env->reserve = (uint64_t)T0;
@@ -328,7 +328,7 @@ void OPPROTO glue(op_ldarx_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu32r, MEMSUFFIX)((uint32_t)T0);
         env->reserve = (uint32_t)T0;
@@ -340,7 +340,7 @@ void OPPROTO glue(op_lwarx_le, MEMSUFFIX) (void)
 void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu32r, MEMSUFFIX)((uint64_t)T0);
         env->reserve = (uint64_t)T0;
@@ -351,7 +351,7 @@ void OPPROTO glue(op_lwarx_le_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu64r, MEMSUFFIX)((uint32_t)T0);
         env->reserve = (uint32_t)T0;
@@ -362,7 +362,7 @@ void OPPROTO glue(op_ldarx_le, MEMSUFFIX) (void)
 void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         T1 = glue(ldu64r, MEMSUFFIX)((uint64_t)T0);
         env->reserve = (uint64_t)T0;
@@ -375,7 +375,7 @@ void OPPROTO glue(op_ldarx_le_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_stwcx, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint32_t)T0)) {
             env->crf[0] = xer_so;
@@ -392,7 +392,7 @@ void OPPROTO glue(op_stwcx, MEMSUFFIX) (void)
 void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint64_t)T0)) {
             env->crf[0] = xer_so;
@@ -408,7 +408,7 @@ void OPPROTO glue(op_stwcx_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_stdcx, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint32_t)T0)) {
             env->crf[0] = xer_so;
@@ -424,7 +424,7 @@ void OPPROTO glue(op_stdcx, MEMSUFFIX) (void)
 void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint64_t)T0)) {
             env->crf[0] = xer_so;
@@ -441,7 +441,7 @@ void OPPROTO glue(op_stdcx_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint32_t)T0)) {
             env->crf[0] = xer_so;
@@ -458,7 +458,7 @@ void OPPROTO glue(op_stwcx_le, MEMSUFFIX) (void)
 void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint64_t)T0)) {
             env->crf[0] = xer_so;
@@ -474,7 +474,7 @@ void OPPROTO glue(op_stwcx_le_64, MEMSUFFIX) (void)
 void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint32_t)T0)) {
             env->crf[0] = xer_so;
@@ -490,7 +490,7 @@ void OPPROTO glue(op_stdcx_le, MEMSUFFIX) (void)
 void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
 {
     if (unlikely(T0 & 0x03)) {
-        do_raise_exception(POWERPC_EXCP_ALIGN);
+        raise_exception(env, POWERPC_EXCP_ALIGN);
     } else {
         if (unlikely(env->reserve != (uint64_t)T0)) {
             env->crf[0] = xer_so;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 68070bf..e9ed627 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -293,10 +293,14 @@ static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
 
 #define GEN_EXCP(ctx, excp, error)                                            \
 do {                                                                          \
+    TCGv_i32 t0 = tcg_const_i32(excp);                                        \
+    TCGv_i32 t1 = tcg_const_i32(error);                                       \
     if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \
         gen_update_nip(ctx, (ctx)->nip);                                      \
     }                                                                         \
-    gen_op_raise_exception_err((excp), (error));                              \
+    gen_helper_raise_exception_err(t0, t1);                                   \
+    tcg_temp_free_i32(t0);                                                    \
+    tcg_temp_free_i32(t1);                                                    \
     ctx->exception = (excp);                                                  \
 } while (0)
 
@@ -3470,7 +3474,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
             }
             if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
                 gen_update_nip(ctx, dest);
-                gen_op_debug();
+                gen_helper_raise_debug();
             }
         }
         tcg_gen_exit_tb(0);
@@ -7233,7 +7237,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
             for (bp = env->breakpoints; bp != NULL; bp = bp->next) {
                 if (bp->pc == ctx.nip) {
                     gen_update_nip(&ctx, ctx.nip);
-                    gen_op_debug();
+                    gen_helper_raise_debug();
                     break;
                 }
             }
@@ -7344,7 +7348,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
     } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
         if (unlikely(env->singlestep_enabled)) {
             gen_update_nip(&ctx, ctx.nip);
-            gen_op_debug();
+            gen_helper_raise_debug();
         }
         /* Generate the return instruction */
         tcg_gen_exit_tb(0);