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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2012-03-27 16:41:55 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2012-04-15 17:07:19 +0200 |
| commit | 52d631dcc70144b6ce8293db78cd6de635331c83 (patch) | |
| tree | 108b08694621ea3fb874f13966ab9a1e4c2b291b /target-ppc | |
| parent | da12872a0973718997c00f1c1e8e5b91ee4c713a (diff) | |
| download | qemu-52d631dcc70144b6ce8293db78cd6de635331c83.zip qemu-52d631dcc70144b6ce8293db78cd6de635331c83.tar.gz qemu-52d631dcc70144b6ce8293db78cd6de635331c83.tar.bz2 | |
PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB
flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
bits at the start of the interrupt handler, the logic towards the end of the
handler to force a TLB flush if either one of these bits were set would never
be triggered.
This patch simply changes the IR/DR bit check in the TLB flush logic to use
the original MSR value (albeit with some interrupt-specific bits cleared) so
that the IR/DR bits are preserved at the point where the check takes place.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c index e13b749..f0ea1c3 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2960,7 +2960,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) if (asrr1 != -1) env->spr[asrr1] = env->spr[srr1]; /* If we disactivated any translation, flush TLBs */ - if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) + if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) tlb_flush(env, 1); if (msr_ile) { |