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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:09:42 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:09:42 +0000 |
| commit | bf8d8ded57a6c54d9ff8a55c35201301ff61ece7 (patch) | |
| tree | 9e3ad19053719095e692f73e0c64c86382b87414 /target-ppc | |
| parent | e343da72b6b99495174f1eeb4af74e70c3147a86 (diff) | |
| download | qemu-bf8d8ded57a6c54d9ff8a55c35201301ff61ece7.zip qemu-bf8d8ded57a6c54d9ff8a55c35201301ff61ece7.tar.gz qemu-bf8d8ded57a6c54d9ff8a55c35201301ff61ece7.tar.bz2 | |
Add lvs{l,r} instructions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/helper.h | 2 | ||||
| -rw-r--r-- | target-ppc/op_helper.c | 18 | ||||
| -rw-r--r-- | target-ppc/translate.c | 32 |
3 files changed, 52 insertions, 0 deletions
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 21a505f..b18f4d2 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -150,6 +150,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) DEF_HELPER_3(vaddcuw, void, avr, avr, avr) DEF_HELPER_3(vsubcuw, void, avr, avr, avr) +DEF_HELPER_2(lvsl, void, avr, tl); +DEF_HELPER_2(lvsr, void, avr, tl); DEF_HELPER_1(efscfsi, i32, i32) DEF_HELPER_1(efscfui, i32, i32) diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 81df85b..9f3ef59 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -1972,6 +1972,24 @@ target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_ for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--) #endif +void helper_lvsl (ppc_avr_t *r, target_ulong sh) +{ + int i, j = (sh & 0xf); + + VECTOR_FOR_INORDER_I (i, u8) { + r->u8[i] = j++; + } +} + +void helper_lvsr (ppc_avr_t *r, target_ulong sh) +{ + int i, j = 0x10 - (sh & 0xf); + + VECTOR_FOR_INORDER_I (i, u8) { + r->u8[i] = j++; + } +} + void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) { int i; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 28ef5af..b1b8009 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6146,6 +6146,38 @@ GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); +GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC) +{ + TCGv_ptr rd; + TCGv EA; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + rd = gen_avr_ptr(rD(ctx->opcode)); + gen_helper_lvsl(rd, EA); + tcg_temp_free(EA); + tcg_temp_free_ptr(rd); +} + +GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC) +{ + TCGv_ptr rd; + TCGv EA; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + rd = gen_avr_ptr(rD(ctx->opcode)); + gen_helper_lvsr(rd, EA); + tcg_temp_free(EA); + tcg_temp_free_ptr(rd); +} + /* Logical operations */ #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ |