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authorAlexander Graf <agraf@suse.de>2012-01-31 03:46:55 +0100
committerAlexander Graf <agraf@suse.de>2012-02-02 02:47:49 +0100
commita496e8eeba51351af136734e475c947a3673dded (patch)
treeefce0e9235f433ab09f73b406e0faa09d3394e4f /target-ppc
parent8917f4dc62a081c684a1769d38c538df94db9cf0 (diff)
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PPC: E500: Populate L1CFG0 SPR
When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: Shrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
-rw-r--r--target-ppc/translate_init.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7848cd7..6253076 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4434,6 +4434,8 @@ static void init_proc_e500 (CPUPPCState *env, int version)
{
uint32_t tlbncfg[2];
uint64_t ivor_mask = 0x0000000F0000FFFFULL;
+ uint32_t l1cfg0 = 0x3800 /* 8 ways */
+ | 0x0020; /* 32 kb */
#if !defined(CONFIG_USER_ONLY)
int i;
#endif
@@ -4485,6 +4487,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
env->dcache_line_size = 64;
env->icache_line_size = 64;
+ l1cfg0 |= 0x1000000; /* 64 byte cache block size */
break;
default:
cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
@@ -4535,7 +4538,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
- 0x00000000);
+ l1cfg0);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,