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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-10-21 11:28:46 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-10-21 11:28:46 +0000
commit3d7b417e13152587df587fe58789740c3ef7abb9 (patch)
tree824bf571e3bad076986e5144f6834ffd032d77f1 /target-ppc/translate_init.c
parentd75a0b97e0e9bfcd73dd2ef081ba06e53932b42d (diff)
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target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually to avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit registers). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate_init.c')
-rw-r--r--target-ppc/translate_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 67951bf..02590ae 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -99,12 +99,12 @@ static void spr_write_clear (void *opaque, int sprn)
/* XER */
static void spr_read_xer (void *opaque, int sprn)
{
- gen_op_load_xer();
+ tcg_gen_mov_tl(cpu_T[0], cpu_xer);
}
static void spr_write_xer (void *opaque, int sprn)
{
- gen_op_store_xer();
+ tcg_gen_mov_tl(cpu_xer, cpu_T[0]);
}
/* LR */