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| author | Tom Musta <tommusta@gmail.com> | 2014-01-07 10:05:51 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:39 +0100 |
| commit | 98d1eb2748e84f9e3118d1bd2495f0cc917ac18d (patch) | |
| tree | 7768c567eff4633cb49b55878c29dc4580dc45de /target-ppc/translate.c | |
| parent | a824bc191a90d86980a9ed090cb1d1219faaf8e7 (diff) | |
| download | qemu-98d1eb2748e84f9e3118d1bd2495f0cc917ac18d.zip qemu-98d1eb2748e84f9e3118d1bd2495f0cc917ac18d.tar.gz qemu-98d1eb2748e84f9e3118d1bd2495f0cc917ac18d.tar.bz2 | |
target-ppc: Add ISA2.06 divdeu[o] Instructions
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used. An architecture
independent 128-bit division routine is added to host-utils.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[agraf: use ||]
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc/translate.c')
| -rw-r--r-- | target-ppc/translate.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f00384b..55f259b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -984,6 +984,20 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); /* divw divw. divwo divwo. */ GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); + +/* div[wd]eu[o][.] */ +#define GEN_DIVE(name, hlpr, compute_ov) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv_i32 t0 = tcg_const_i32(compute_ov); \ + gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ + cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ + tcg_temp_free_i32(t0); \ + if (unlikely(Rc(ctx->opcode) != 0)) { \ + gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ + } \ +} + #if defined(TARGET_PPC64) static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, int sign, int compute_ov) @@ -1032,6 +1046,10 @@ GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); /* divw divw. divwo divwo. */ GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); + +GEN_DIVE(divdeu, divdeu, 0); +GEN_DIVE(divdeuo, divdeu, 1); + #endif /* mulhw mulhw. */ @@ -9707,6 +9725,9 @@ GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), +GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), +GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), + #undef GEN_INT_ARITH_MUL_HELPER #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |