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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-30 16:24:30 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2008-11-30 16:24:30 +0000
commitbdb4b68907a88090148c5ab9aea17b67f9ef2542 (patch)
tree7bf16c7549abe5d73495817581befc3755b26f3a /target-ppc/translate.c
parentdfbc799d8e94d26ab2e6ad4a65dc97fd8fb6ece6 (diff)
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target-ppc: convert lscbx instruction to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-ppc/translate.c')
-rw-r--r--target-ppc/translate.c45
1 files changed, 12 insertions, 33 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 91c0f3d..f97a3ed 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4526,47 +4526,26 @@ GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
}
-/* As lscbx load from memory byte after byte, it's always endian safe.
- * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
- */
-#define op_POWER_lscbx(start, ra, rb) \
-(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
-#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
-#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
-#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
-#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
-#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
-#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
-static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
- GEN_MEM_FUNCS(POWER_lscbx),
-};
-
/* lscbx - lscbx. */
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
{
- int ra = rA(ctx->opcode);
- int rb = rB(ctx->opcode);
+ TCGv t0 = tcg_temp_new();
+ TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
+ TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
+ TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
- gen_addr_reg_index(cpu_T[0], ctx);
- if (ra == 0) {
- ra = rb;
- }
+ gen_addr_reg_index(t0, ctx);
/* NIP cannot be restored if the memory exception comes from an helper */
gen_update_nip(ctx, ctx->nip - 4);
- tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
- tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
- tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
- op_POWER_lscbx(rD(ctx->opcode), ra, rb);
+ gen_helper_lscbx(t0, t0, t1, t2, t3);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
- tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
+ tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_T[0]);
+ gen_set_Rc0(ctx, t0);
+ tcg_temp_free(t0);
}
/* maskg - maskg. */