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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2014-12-13 19:48:18 +0300 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-16 18:43:19 +0000 |
| commit | 339aaf5b7f26d1e638641c59a44883b7654bd8ea (patch) | |
| tree | 43aa54e232bce6e2ece131bfff379a73ed057650 /target-ppc/mmu-hash32.c | |
| parent | d86fb03469e016af4e54f04efccbc20a8afa3e19 (diff) | |
| download | qemu-339aaf5b7f26d1e638641c59a44883b7654bd8ea.zip qemu-339aaf5b7f26d1e638641c59a44883b7654bd8ea.tar.gz qemu-339aaf5b7f26d1e638641c59a44883b7654bd8ea.tar.bz2 | |
qemu-log: add log category for MMU info
Running barebox on qemu-system-mips* with '-d unimp' overloads
stderr by very very many mips_cpu_handle_mmu_fault() messages:
mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 00000000180003fd prot 3
mips_cpu_handle_mmu_fault address=a0800884 ret 0 physical 0000000000800884 prot 3
mips_cpu_handle_mmu_fault pc a080cd80 ad b80003fd rw 0 mmu_idx 0
So it's very difficult to find LOG_UNIMP message.
The mips_cpu_handle_mmu_fault() messages appear on enabling ANY
logging! It's not very handy.
Adding separate log category for *_cpu_handle_mmu_fault()
logging fixes the problem.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1418489298-1184-1-git-send-email-antonynpavlov@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-ppc/mmu-hash32.c')
| -rw-r--r-- | target-ppc/mmu-hash32.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 0a13a81..dfee358 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -28,10 +28,8 @@ //#define DEBUG_BAT #ifdef DEBUG_MMU -# define LOG_MMU(...) qemu_log(__VA_ARGS__) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) #else -# define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0) #endif @@ -225,7 +223,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, CPUState *cs = CPU(ppc_env_get_cpu(env)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); - LOG_MMU("direct store...\n"); + qemu_log_mask(CPU_LOG_MMU, "direct store...\n"); if ((sr & 0x1FF00000) >> 20 == 0x07f) { /* Memory-forced I/O controller interface access */ @@ -348,12 +346,13 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env, ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ - LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx + " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); /* Primary PTEG lookup */ - LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " ptem=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, hash); @@ -361,7 +360,7 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env, pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte); if (pte_offset == -1) { /* Secondary PTEG lookup */ - LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx " vsid=%" PRIx32 " api=%" PRIx32 " hash=" TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, vsid, ptem, ~hash); @@ -476,7 +475,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); + qemu_log_mask(CPU_LOG_MMU, + "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); /* 7. Check access permissions */ @@ -484,7 +484,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, if (need_prot[rwx] & ~prot) { /* Access right violation */ - LOG_MMU("PTE access rejected\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); if (rwx == 2) { cs->exception_index = POWERPC_EXCP_ISI; env->error_code = 0x08000000; @@ -501,7 +501,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx, return 1; } - LOG_MMU("PTE access granted !\n"); + qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); /* 8. Update PTE referenced and changed bits if necessary */ |